add urukul sync

master
ciciwu 2022-02-10 16:28:31 +08:00
parent e4b35547d3
commit a43e83c648
3 changed files with 16 additions and 8 deletions

View File

@ -11,25 +11,29 @@
"type": "urukul",
"dds": "ad9912",
"ports": [1, 2],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [3, 4],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [5, 6],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [7, 8],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "dio",

View File

@ -35,7 +35,8 @@
"type": "urukul",
"dds": "ad9910",
"ports": [4, 5],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "dio",

View File

@ -13,19 +13,22 @@
"type": "urukul",
"dds": "ad9910",
"ports": [1, 2],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [3],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "urukul",
"dds": "ad9912",
"ports": [4],
"clk_sel": 2
"clk_sel": 2,
"synchronization": true
},
{
"type": "sampler",