Browse Source

add roa1master roa1satellite

master
Robert Jördens 1 year ago
parent
commit
a42b7e27dc
  1. 1
      npl3satellite.json
  2. 84
      roa1master.json
  3. 25
      roa1satellite.json

1
npl3satellite.json

@ -4,7 +4,6 @@
"min_artiq_version": "6.0",
"variant": "npl3satellite",
"hw_rev": "v2.0",
"ext_ref_frequency": 10e6,
"base": "satellite",
"vendor": "QUARTIQ",
"peripherals": [

84
roa1master.json

@ -0,0 +1,84 @@
{
"_description": "ROA Alvarez",
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "roa1master",
"hw_rev": "v2.0",
"ext_ref_frequency": 10e6,
"base": "master",
"core_addr": "10.34.16.100",
"vendor": "QUARTIQ",
"peripherals": [
{
"type": "dio",
"board": "DIO_SMA",
"ports": [0],
"hw_rev": "v1.2",
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [1],
"hw_rev": "v1.2",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [2],
"hw_rev": "v1.2",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [3],
"hw_rev": "v1.2",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [4],
"hw_rev": "v1.2",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [5],
"hw_rev": "v1.2",
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "sampler",
"hw_rev": "v2.2",
"ports": [6, 7]
},
{
"type": "urukul",
"hw_rev": "v1.5",
"ports": [8, 9],
"clk_sel": 2,
"synchronization": true
},
{
"type": "mirny",
"hw_rev": "v1.1",
"ports": [10],
"clk_sel": "mmcx"
},
{
"type": "zotino",
"hw_rev": "v1.5",
"ports": [11]
}
]
}

25
roa1satellite.json

@ -0,0 +1,25 @@
{
"_description": "ROA Alvarez, Master is roa1master",
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "roa1satellite",
"hw_rev": "v2.0",
"base": "satellite",
"vendor": "QUARTIQ",
"peripherals": [
{
"type": "suservo",
"sampler_ports": [0, 1],
"urukul0_ports": [2, 3],
"urukul1_ports": [4, 5],
"clk_sel": 2
},
{
"type": "suservo",
"sampler_ports": [6, 7],
"urukul0_ports": [8, 9],
"urukul1_ports": [10, 11],
"clk_sel": 2
}
]
}
Loading…
Cancel
Save