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siassatellite->ustc4, sias2->siassatellite

master
ciciwu 12 months ago
parent
commit
2d745615a9
  1. 35
      siassatellite.json
  2. 39
      ustc4.json

35
siassatellite.json

@ -7,32 +7,43 @@
"peripherals": [
{
"type": "dio",
"board": "DIO_SMA",
"ports": [0],
"edge_counter": true,
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"board": "DIO_SMA",
"ports": [1],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "suservo",
"sampler_ports": [2, 3],
"urukul0_ports": [4, 5],
"urukul1_ports": [6, 7],
"clk_sel": 2
"type": "dio",
"board": "DIO_SMA",
"ports": [2],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [8, 9],
"clk_sel": 2
"type": "dio",
"board": "DIO_SMA",
"ports": [3],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "fastino",
"ports": [10]
"ports": [4]
},
{
"type": "suservo",
"sampler_ports": [10, 11],
"urukul0_ports": [6, 7],
"urukul1_ports": [8, 9],
"clk_sel": 2
}
]
}
]
}

39
ustc4.json

@ -0,0 +1,39 @@
{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "ustc4",
"hw_rev": "v2.0",
"base": "standalone",
"core_addr": "192.168.1.75",
"peripherals": [
{
"type": "dio",
"ports": [0],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [1],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "suservo",
"sampler_ports": [2, 3],
"urukul0_ports": [4, 5],
"urukul1_ports": [6, 7],
"clk_sel": 2
},
{
"type": "urukul",
"dds": "ad9910",
"ports": [8, 9],
"clk_sel": 2
},
{
"type": "fastino",
"ports": [10]
}
]
}
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