From 2714a5695b2c56de96c9f6c8adfb5c6be4b4f021 Mon Sep 17 00:00:00 2001 From: Zheng-Jiakun Date: Thu, 19 Aug 2021 09:51:23 +0800 Subject: [PATCH] add ucla2 --- ucla2.json | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 ucla2.json diff --git a/ucla2.json b/ucla2.json new file mode 100644 index 0000000..e63d8a1 --- /dev/null +++ b/ucla2.json @@ -0,0 +1,55 @@ +{ + "target": "kasli", + "min_artiq_version": "6.0", + "variant": "ucla2", + "hw_rev": "v2.0", + "base": "standalone", + "core_addr": "192.168.1.75", + "peripherals": [ + { + "type": "grabber", + "ports": [0] + }, + { + "type": "dio", + "board": "DIO_BNC", + "hw_rev": "v1.4", + "ports": [1], + "bank_direction_low": "input", + "bank_direction_high": "output" + }, + { + "type": "dio", + "board": "DIO_BNC", + "hw_rev": "v1.4", + "ports": [2], + "bank_direction_low": "output", + "bank_direction_high": "output" + }, + { + "type": "dio", + "board": "DIO_BNC", + "hw_rev": "v1.4", + "ports": [3], + "bank_direction_low": "output", + "bank_direction_high": "output" + }, + { + "type": "suservo", + "sampler_ports": [10, 11], + "urukul0_ports": [4, 5], + "urukul1_ports": [6, 7], + "clk_sel": 2 + }, + { + "type": "phaser", + "ports": [8], + "clk_sel": 2 + }, + { + "type": "fastino", + "hw_rev": "v1.1", + "ports": [9] + } + ] +} \ No newline at end of file