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sinara-systems-legacy
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add ustc5master

master
ciciwu213 2021-09-14 16:38:51 +08:00
parent 31d9238174
commit 1beaa45db5
1 changed files with 67 additions and 0 deletions
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ustc5master.json Normal file
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{
"target": "kasli",
"min_artiq_version": "6.0",
"variant": "ustc5master",
"hw_rev": "v2.0",
"base": "master",
"core_addr": "192.168.1.75",
"peripherals": [
{
"type": "dio",
"ports": [0],
"bank_direction_low": "input",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [1],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [2],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [3],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [4],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [5],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [6],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "dio",
"ports": [7],
"bank_direction_low": "output",
"bank_direction_high": "output"
},
{
"type": "fastino",
"ports": [8]
},
{
"type": "sampler",
"hw_rev": "v2.2",
"ports": [10, 11]
}
]
}