From 1beaa45db55d4327c429440b5edffdd0f7189669 Mon Sep 17 00:00:00 2001
From: ciciwu213 <yw@m-labs.hk>
Date: Tue, 14 Sep 2021 16:38:51 +0800
Subject: [PATCH] add ustc5master

---
 ustc5master.json | 67 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 67 insertions(+)
 create mode 100644 ustc5master.json

diff --git a/ustc5master.json b/ustc5master.json
new file mode 100644
index 0000000..238172f
--- /dev/null
+++ b/ustc5master.json
@@ -0,0 +1,67 @@
+{
+    "target": "kasli",
+    "min_artiq_version": "6.0",
+    "variant": "ustc5master",
+    "hw_rev": "v2.0",
+    "base": "master",
+    "core_addr": "192.168.1.75",
+    "peripherals": [
+        {
+            "type": "dio",
+            "ports": [0],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [3],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [4],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [5],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [6],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [7],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "fastino",
+            "ports": [8]
+        },
+        {
+            "type": "sampler",
+            "hw_rev": "v2.2",
+            "ports": [10, 11]
+        }
+    ]
+}