From 16ada506ae1804ea06b631cafc9d37d329c79ccf Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Fri, 15 Jan 2021 13:00:24 +0800
Subject: [PATCH] add stfc master + satellite

---
 stfcmaster.json    | 47 ++++++++++++++++++++++++++++++++++++++++++++++
 stfcsatellite.json | 40 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+)
 create mode 100644 stfcmaster.json
 create mode 100644 stfcsatellite.json

diff --git a/stfcmaster.json b/stfcmaster.json
new file mode 100644
index 0000000..153448b
--- /dev/null
+++ b/stfcmaster.json
@@ -0,0 +1,47 @@
+{
+    "target": "kasli",
+    "variant": "stfcmaster",
+    "hw_rev": "v2.0",
+    "base": "master",
+    "core_addr": "192.168.1.75",
+    "peripherals": [
+        {
+            "type": "grabber",
+            "ports": [0, 1, 2]
+        },
+        {
+            "type": "dio",
+            "ports": [3],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [4],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [5],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [6],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9912",
+            "ports": [7, 8],
+            "clk_sel": 2
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        }
+    ]
+}
\ No newline at end of file
diff --git a/stfcsatellite.json b/stfcsatellite.json
new file mode 100644
index 0000000..9939edf
--- /dev/null
+++ b/stfcsatellite.json
@@ -0,0 +1,40 @@
+{
+    "target": "kasli",
+    "variant": "stfcsatellite",
+    "hw_rev": "v2.0",
+    "base": "satellite",
+    "peripherals": [
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [0, 1],
+            "clk_sel": 2
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [2, 3],
+            "clk_sel": 2
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [4, 5],
+            "clk_sel": 2
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [6, 7],
+            "clk_sel": 2
+        },
+		{
+            "type": "sampler",
+            "ports": [8, 9]
+        },
+        {
+            "type": "sampler",
+            "ports": [10, 11]
+        }
+    ]
+}