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Joe Britton 2019-01-14 11:20:03 -05:00
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# saymapp
Sayma Project Plan

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# Hardware Developer
The Hardware Developer is responsible for hardware design and manufacturing. Testing responsibilities of the Hardware Developer are those detailed in HT3.
The Hardware Developer has deliverables designated HTn. Written progress reports
- on the 1st and 15th of the month
The Hardware Developer has deliverables designated HTn. Written progress reports by the 1st of the month.
## __HT1__ high level design
High-level schematics for all PCBs to include component part numbers, high-level component interconnection, power budget, high-level layout of all PCBs including location of ICs, board-to-board headers, RF shielding, heat sinks, mechanical support and front panel design. Post design files to github and tag. Participate in design review on github.
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# Integration and Timing Developer
An Integration and Timing Developer is responsible for certain aspects of hardware integration and testing as detailed in this section.
This developer has one deliverable OT1. Written progress reports
- on the 1st and 15th of the month
This developer has one deliverable OT1. Written progress reports by the 1st of the month.
## __OT1__ integration and timing
@ -368,9 +366,7 @@ The Software and Gateware Developer is responsible for gateware and software nee
All MTk items include support of code in ARTIQ for 3 years from start of contract including documentation of public APIs, maintenance of developed CI infrastructure, publication of CI results.
The developer’s work consists of deliverables MTk below. Written progress reports are due
- on 1st and 15th of the month
- on 1st of the month after OT1 and HT5 are complete
The developer’s work consists of deliverables MTk below. Written progress reports are due by the 1st of the month.
## __MT1__ SAWG