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switch to ADF4356 as primary synth; retain HMC830 in clock tree

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Joe Britton 2019-01-14 16:24:05 -05:00
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@ -93,10 +93,13 @@ This is an extension of SAWG v2.0 that includes improvements in performance and
# Sayma v2 Diffs
When diff also applies for [Metlino](https://github.com/sinara-hw/Metlino/issues) it is noted.
## RTM Synthesizer
As per discussion on [20190111](https://github.com/sinara-hw/sinara/wiki/Minutes20190111-Sayma-v2)
- Layout both ADF4356 and HMC830
- Use ADF4356 as primary synthesizer, HMC830 is backup
- Use ADCLK948 to multiplex
## Clock recovery and synthesizer
[TODO
I don't know how to reconcile requests to freeze the design with well motivated but invasive requests to change the design. Let's discuss how to proceed at a programatic level at the Friday conference call.
@ -325,10 +328,12 @@ Code submitted for inclusion in ARTIQ shall comply with CONTRIBUTING.rst (https:
- __O14__ Based on O11, demonstrate ST4 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1.
- Write and document code. Generate pull request.
- __O15__ write and test ADF4356 driver
- __O15__ ADF4356
- Measure phase determinism of ADF4356.
- Write and test ADF4356 driver.
- Write and document code. Generate pull request.
- __O16__ in support of a future clock distribution scheme modeled after White Rabbit (WR), specify layout of Si549 and related components
- __O16__ in support of a future clock distribution scheme modeled after White Rabbit (WR, DDMTD), specify layout of Si549 and related components
[TODO: How to support this if at all? - Write and document code. Generate pull request.]
@ -417,8 +422,7 @@ Each MTk includes a short report and option to implement.
## __MT3__ Sayma v2 ARTIQ Support
- __M31__ Review the code emerging from O14 and O15. Support merge into ARTIQ. Aspects included in review: DRTIO-on-RTM, DRTIO clock
recovery on RTM, JESD204B deterministic latency/synchronization.
- __M31__ Review the code emerging from O14 and O15. Support merge into ARTIQ. Aspects included in review: DRTIO-on-RTM, DRTIO clock recovery on RTM, JESD204B deterministic latency/synchronization.
[TODO: does this include DDMTD?]
- __M32__ Work with TPOC to develop test cases for SAWG v2.1 with ST1 and ST2 in mind. Split into manual test cases and tests amendable to continuous integration (CI). Procure hardware needed for hardware-in-the-loop tests.