diff --git a/pp.md b/pp.md
index fcedde2..65c30e8 100644
--- a/pp.md
+++ b/pp.md
@@ -109,11 +109,8 @@ As per discussion on [20190111](https://github.com/sinara-hw/sinara/wiki/Minutes
 - Use ADCLK948 to multiplex 
 
 
-[TODO 
-I don't know how to reconcile requests to freeze the design with  well motivated but invasive requests to change the design. Let's discuss how to proceed at a programatic level at the Friday conference call. 
-
-https://github.com/sinara-hw/Sayma_RTM/issues/16#issuecomment-452661542
-]
+## DDMTD 
+Implement DDMTD (White Rabbit) clock recovery on both AMC and RTM. 
 
 ## DAC-FPGA Synchronization
 Deterministic phase alignment between DACs on separate Sayma PCBs between power cycles is an important design criterion and should be considered at all stages of design. This implies a) SYSREF is aligned with RTIO clock b) DAC clocks are synchronized to local SYSREF edges.