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minor edits requested by Creotech

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Joe Britton 2019-03-07 18:07:43 -05:00
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pp.md
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@ -22,6 +22,8 @@ The design review consists of three steps: HT1, HT1.5 and HT2. The Hardware Deve
The Software and Gateware Developer and Integration and Timing Developer have tasks which depend on proper functionality of the Sayma v2 hardware. The Hardware Developer testing and reporting expectations are detailed in HT3.
The Hardware Developer shall establish a financial reserve sufficient to stuff up to two replacement PCBs in the case of catastrophic damage or shipping loss in the course of collaboration with other Developers.
### Flaw found in HT3
If the HT3 report indicates a failing component or subsystem, a Developer working on a dependent task may at its option pursue the following options
@ -231,7 +233,7 @@ Fabricate PCBs in the following quantities. TPOC provides sign off prior to comm
UMD shall loan the following parts to Hardware Developer at the start of HT3. They will be returned to UMD at the close of HT5.
- 1 NAT NATIVE-R5
- 2 NAT AC 600D
- 1 NAT AC 600D
- 1 NAT MCH-Basic v3.5
Expectations for testing of all stuffed PCBs.
@ -241,8 +243,8 @@ Expectations for testing of all stuffed PCBs.
- https://github.com/sinara-hw/Metlino
- https://github.com/sinara-hw/BaseMod
- thermal test in TS7
- goal: maximum temperature of any IC 65 C
- Monitor temperature of several representative ICs using MMC IPMI
- goal: maximum temperature of measured ICs < 65 C
- Monitor temperature of a subset of ICs using MMC IPMI.
- crate power-on with all boards and with arbitrary RTM unplugged in TS7
- hot swap arbitrary AMC and RTM boards in TS7
- power-on with or without RTM unplugged in TS1
@ -284,7 +286,11 @@ HT3 delivery is complete when the Software and Gateware Developer and Integratio
- Embed link in github that links to readthedocs.
- scope: expected content is superset of existing Sayma v1 documentation
- scope: documentation to also include the following github Issues
https://github.com/sinara-hw/sinara/issues?q=is%3Aissue+documentation+label%3Aarea%3Adocumentation+is%3Aopen
- [https://github.com/sinara-hw/sinara/issues/518](https://github.com/sinara-hw/sinara/issues/518)
- [https://github.com/sinara-hw/sinara/issues/477](https://github.com/sinara-hw/sinara/issues/477)
- [https://github.com/sinara-hw/sinara/issues/476](https://github.com/sinara-hw/sinara/issues/476)
- [https://github.com/sinara-hw/sinara/issues/435](https://github.com/sinara-hw/sinara/issues/435)
- [https://github.com/sinara-hw/sinara/issues/433](https://github.com/sinara-hw/sinara/issues/433)
HT4 delivery is complete when documentation and source is committed and accepted by TPOC.
@ -298,7 +304,7 @@ Build demonstration system that is fully assembled and tested. The system shall
- ST1, ST2, ST3 and ST4
- Use SAWG >= 2.0
- Ship demonstration system to UMD.
- UMD/ARL will return TS-MTCA and clock hardware to the Hardware Developer 1 month after delivery. All other parts will remain property of UMD.
- UMD/ARL will return clock hardware to the Hardware Developer 1 month after delivery. All other parts will remain property of UMD.
HT5 delivery is complete when UMD confirms receipt of the demonstration system /and/ TPOC successfully runs test code. TPOC has 7 business days to conduct tests.