diff --git a/pp.md b/pp.md
index cdf2eaa..e62231f 100644
--- a/pp.md
+++ b/pp.md
@@ -80,7 +80,7 @@ The original SAWG was developed by M-Labs for Sayma v1.0. Here, "v1" refers to S
     - 240 MHz is max RF out 
     - f1, f2: 150 MHz modulation, +/- 60 MHz anti-aliasing filter bandwidth
 
-__SAWG v2.0 milestone__
+__SAWG v2.0 milestone_
 
 This is an extension of SAWG v1.0 with a 1 GSPS data rate.  This milestone also includes board-board synchronization. 
 - f_rtio = f_dac_ref = 125 MHz (same as for Kasli)
@@ -333,7 +333,7 @@ Code submitted for inclusion in ARTIQ shall comply with CONTRIBUTING.rst (https:
 
 - __O1.03__ participate in HT2 design review
 
-- __O1.04__ based on O1.01, ensure passage of ST3 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1. Note that this test is short of the full ST3 test which specifies a pair of Sayma v2 boards. 
+- __O1.04_ based on O1.01, ensure passage of ST3 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1. Note that this test is short of the full ST3 test which specifies a pair of Sayma v2 boards. 
     - Write and document code. Generate pull request.
 
 - __O1.05__ ADF4356
@@ -357,8 +357,6 @@ The Software and Gateware Developer is responsible for gateware and software nee
 - Documentation of design choices 
 - Documentation of code functionality
 
-All MTk items include support of code in ARTIQ for 3 years from start of contract including documentation of public APIs, maintenance of developed CI infrastructure, publication of CI results. 
-
 The developer’s work consists of deliverables MTk below. Written progress reports are due by the 1st of the month.
 
 ## __MT1__ SAWG
@@ -404,7 +402,7 @@ Each MTk includes a short report and option to implement.
 
 - __M2.03__ Review of the scheme for synchronization between pairs of Sayma boards and complete clocking scheme.
 
-- __M2.04__ SDRAM test suite
+- __ M2.04__ SDRAM test suite
 
 In support of HT3 tests conducted by Hardware Developer, write
 gateware module to test SDRAM power consumption and signal integrity. 
@@ -444,7 +442,7 @@ Adapt to be included in ARTIQ built-in self-test suite.
     - boot tasks including slave serial loading of FPGA
     - RTM clocking
     - develop DRTIO for AMC FPGA to RTM FPGA link
-    - SPI to HMC830 and AD9154
+    - SPI to HMC830
     - AFE interfaces
     - build infrastructure and packaging
     - dependency: M3.03
@@ -479,12 +477,13 @@ Adapt to be included in ARTIQ built-in self-test suite.
         - SAWG v2.1 ARTIQ Python API
         - document underlying DSP architecture
 
-- __M3.10__ DRTIO for RTM
-    - in Sayma v1.0 serwb was developed for communication between AMC FPGA and RTM FPGA
-    - replace serwb with pure DRTIO link
-
 - __M3.11__ Support Hardware Developer on HT5
 
+- __M3.12__ Long term support
+    - Maintenance of Sayma v2 code in ARTIQ for 3 years. 
+    - Includes documentation of public APIs, maintenance of developed CI infrastructure and publication of CI results. 
+    - Maintenance interval commences after baseline support for Sayma v2 ships.  
+
 ----------
 
 # Project Organization