diff --git a/pp.md b/pp.md index 3194309..395446b 100644 --- a/pp.md +++ b/pp.md @@ -379,23 +379,23 @@ MT1 is a port of SAWG v1.0 designed for Sayma v1 to Sayma v2. Additional improve Each MTk includes a short report and option to implement. -- __M11__ Support SAWG v2.0 +- __M1.01__ Support SAWG v2.0 - Develop code for Sayma v2 SAWG+JESD+fpga clock tree at 1 GSPS. - Implement new Sayma v2 sysref synchronization scheme. -- __M12__ SAWG v2.1 element: Measure resource usage and limit number of channels if unable to fit. +- __M1.02__ SAWG v2.1 element: Measure resource usage and limit number of channels if unable to fit. -- __M13__ SAWG v2.1 element: Evaluate clocking SAWG or parts of it at 250 MHz (2x f_rtio) +- __M1.03__ SAWG v2.1 element: Evaluate clocking SAWG or parts of it at 250 MHz (2x f_rtio) -- __M14__ SAWG v2.1 element: Determine number of CORDIC stages, width, phase resolution to achieve a specified spur suppression under specified conditions +- __M1.04__ SAWG v2.1 element: Determine number of CORDIC stages, width, phase resolution to achieve a specified spur suppression under specified conditions -- __M15__ SAWG v2.1 element: Design transaction based SAWG RTIO protocol (rewrite protocol to stage interpolator settings over one or few non-concurrent RTIO output channels, then activate synchronously with a single RTIO output event). Discuss and determine data partitioning among interpolators and SAWG channels. +- __M1.05__ SAWG v2.1 element: Design transaction based SAWG RTIO protocol (rewrite protocol to stage interpolator settings over one or few non-concurrent RTIO output channels, then activate synchronously with a single RTIO output event). Discuss and determine data partitioning among interpolators and SAWG channels. -- __M16__ SAWG v2.1 element: Design fractional representation of high-order spline interpolator coefficients (i.e. instead of 64 bits, just 16 denominator + 16 numerator bits for the 3rd order spline coefficient). This also allows getting rid of the SAWG clock stretcher that was never officially supported. +- __M1.06__ SAWG v2.1 element: Design fractional representation of high-order spline interpolator coefficients (i.e. instead of 64 bits, just 16 denominator + 16 numerator bits for the 3rd order spline coefficient). This also allows getting rid of the SAWG clock stretcher that was never officially supported. -- __M17__ SAWG v2.1 element: Evaluate SAWG DUC redesign with 3 or 4 bit frequency and phase resolution based on multipliers instead of parallel cordics. +- __M1.07__ SAWG v2.1 element: Evaluate SAWG DUC redesign with 3 or 4 bit frequency and phase resolution based on multipliers instead of parallel cordics. -- __M18__ SAWG v2.1 element: Evaluate resource consumption of modulation ports for after spline interpolators. +- __M1.08__ SAWG v2.1 element: Evaluate resource consumption of modulation ports for after spline interpolators. - Multiplicative for amplitude, additive and saturating for frequency and phase. - No support for configurable clipping amplitude at modulation summing junctions. Clipping is always on. @@ -404,9 +404,9 @@ Each MTk includes a short report and option to implement. ## __MT2__ Sayma v2 Planning -- __M21__ Develop fixed test pattern generator (12-point cosine on odd channels and ramps with major carry toggles on even channels) as a compile time alternative to SAWG. +- __M2.01__ Develop fixed test pattern generator (12-point cosine on odd channels and ramps with major carry toggles on even channels) as a compile time alternative to SAWG. -- __MT22__ Review and verify Sayma v2 design from the FPGA perspective. Do this by building a stub ARTIQ target and test compilation -- depends on obtaining netlist for FPGAs from Hardware Developer (HT2). This will verify IO assignments and usage patterns around the following subsystems to the level currently used in ARTIQ +- __M2.02__ Review and verify Sayma v2 design from the FPGA perspective. Do this by building a stub ARTIQ target and test compilation -- depends on obtaining netlist for FPGAs from Hardware Developer (HT2). This will verify IO assignments and usage patterns around the following subsystems to the level currently used in ARTIQ - ethernet - transceivers - clocking @@ -416,8 +416,22 @@ Each MTk includes a short report and option to implement. - AFE ports - FMC ports -- __MT23__ Review of the scheme for synchronization between pairs of Sayma boards and complete clocking scheme. +- __M2.03__ Review of the scheme for synchronization between pairs of Sayma boards and complete clocking scheme. +- __ M2.04__ SDRAM test suite + +In support of HT3 tests conducted by Hardware Developer, write +gateware module to test SDRAM power consumption and signal integrity. +The test shall be developed in coordination with Hardware Developer and with +their HT3 test workflow in mind. +- maximum I/O bandwidth (64Gbps), refresh disabled +- continuous precharge/activate cycles in one bank at the maximum rate +permitted by the chip and the available command bandwidth +- continuous data transfers on other banks with the following pattern + - 0x5555... / 0xaaaa... to test for cross talk + - 0xffff... / 0x0000... to test for ground bounce + - one row in the data test bank permanently open +Adapt to be included in ARTIQ built-in self-test suite. ## __MT3__ Sayma v2 ARTIQ Support