From 2f56e4d7bf1a71f60a6f7cbae2c814df90ec71f6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?S=C3=A9bastien=20Bourdeauducq?= <sb@m-labs.hk>
Date: Fri, 18 Jan 2019 23:20:52 +0800
Subject: [PATCH] Update pp.md

---
 pp.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/pp.md b/pp.md
index 2143c18..dd2012f 100644
--- a/pp.md
+++ b/pp.md
@@ -254,7 +254,8 @@ Expectations for testing of all stuffed PCBs.
     - AD built-in DAC JESD PRBS test at 10 Gb/s lane for both DACs
     - SDRAM PRBS write-then-read at [TODO ____ data rate]
     - AMC backplane ethernet PRBS at 1 GSPS
-    - SFP loop-back PRBS at 1 Gb/s
+    - SFP loop-back PRBS at 6 Gb/s
+    - AMC backplane PRBS at 6 Gb/s
     - FMC loop-back PRBS [TODO ____ data rate]
     - Realistic FPGA fabric load and clock activity
 - MMC configuration including power supply sequencing and IPMI