diff --git a/pp.md b/pp.md
index 24032f7..96132b5 100644
--- a/pp.md
+++ b/pp.md
@@ -80,7 +80,7 @@ This is an extension of SAWG v1.0 with a 1 GSPS data rate.  This milestone also
 - f_rtio = f_dac_ref = 125 MHz (same as for Kasli)
 - dac data rate 1.0 GSPS
 - f_dac_clk = 2.0 GHz (2X interpolation) 
-- synchronization: new Sayma v2 sysref scheme
+- synchronization: new Sayma v2 sysref scheme, ST3
 - support 2 RF channels per DAC (!)
 - functionality in 1st Nyquist
     - 400 MHz is max RF out 
@@ -258,7 +258,7 @@ Expectations for testing of all stuffed PCBs.
     - AMC backplane ethernet PRBS at 1 GSPS
     - SFP loop-back PRBS at 6 Gb/s
     - AMC backplane PRBS at 6 Gb/s
-    - FMC loop-back PRBS [TODO ____ data rate]
+    - FMC loop-back 
     - Realistic FPGA fabric load and clock activity
 - MMC configuration including power supply sequencing and IPMI
     - Hardware Developer shall test MMC firmware on TS7 system prior to distribution.
@@ -321,13 +321,13 @@ Dependency: Software and Gateware Developer is responsible for supplying AD9154
 
 Code submitted for inclusion in ARTIQ shall comply with CONTRIBUTING.rst (https://github.com/m-labs/artiq/blob/master/CONTRIBUTING.rst). 
 
-- __O1.01__ implement DAC-FPGA synchronization with 2 GHz DAC clock (1 GSPS data rate).
+- __O1.01__ implement DAC-FPGA synchronization with 2 GHz DAC clock (1 GSPS data rate) with ST3 in mind
 
 - __O1.02__ participate in HT1 and HT1.5 design reviews
 
 - __O1.03__ participate in HT2 design review
 
-- __O1.04_ Based on O11, demonstrate ST4 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1.
+- __O1.04_ based on O1.01, ensure passage of ST3 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1. Note that this test is short of the full ST3 test which specifies a pair of Sayma v2 boards. 
     - Write and document code. Generate pull request.
 
 - __O1.05__ ADF4356
@@ -441,29 +441,28 @@ Adapt to be included in ARTIQ built-in self-test suite.
     - SPI to HMC830 and AD9154
     - AFE interfaces
     - build infrastructure and packaging
-    - dependency: M33
+    - dependency: M3.03
 
 - __M3.05__ Support for BaseMod to include the following
     - attenuator shift register
     - DRTIO control of RF switches using TTL PHY
-    - dependency: M34
+    - dependency: M3.04
 
 - __M3.06__ Validate RF output using SAWG v1.0. This tests operation of SAWG as developed for Sayma v1 works on Sayma v2. It tests the following elements.  
     - clocking of AD9154
     - SYSREF syncing of DAC and JESD core
     - JESD204B to AD9154
     - SAWG v1.0 integration
-    - dependency: M34
+    - dependency: M3.04
 
 - __M3.07__ SAWG v2.0
-    - ensure passage of tests ST1, ST2 and ST4
-    - Double check ST3 using code supplied under task O14
-    - dependencies: M36, O14
+    - ensure passage of tests ST1, ST2, ST3 and ST4
+    - dependencies: M3.06, O1.04
 
 - __M3.08__ SAWG v2.1  
     - ensure proper implementation of features in SAWG v2.1
     - confirm that ST1, ST2, ST3 and ST4 tests still pass
-    - dependency: M37
+    - dependency: M3.07
 
 - __M3.09__ Documentation 
     - integrate manual and automated CI tests into ARTIQ infrastructure