This plan defines concrete performance goals, specifies which parties are responsible for specific deliverables and defines a project management structure. The aim is to provide sufficient specification and structure at the outset that all parties feel comfortable with their responsibilities and minimizes conflict.
The plan includes design choices that simplify Sayma and lower costs. The github Sayma Issue tracking contains a long list of bug fixes and modifications to v1 (https://github.com/sinara-hw/sinara). The plan calls out explicit specifications in cases where there is not a clear consensus in the Issues.
Developer tasks are labeled HTj, Oj.k and Mj.k (jk integers) and are not divisible. If a task or feature is not assigned to a Developer then that Developer is not responsible for it.
The design review consists of three steps: HT1, HT1.5 and HT2. The Hardware Developer has primary responsibility for the design review. Certain review tasks are delegated to other Developers as detailed below. Tracking of design review tasks is in a google docs spreadsheet communicated under separate cover.
## Handling Hardware Flaws
The Software and Gateware Developer and Integration and Timing Developer have tasks which depend on proper functionality of the Sayma v2 hardware. The Hardware Developer testing and reporting expectations are detailed in HT3.
The Hardware Developer shall establish a financial reserve sufficient to stuff up to two replacement PCBs in the case of catastrophic damage or shipping loss in the course of collaboration with other Developers.
If the HT3 report indicates a failing component or subsystem, a Developer working on a dependent task may at its option pursue the following options
- cancel dependent task(s)
- renegotiate contract terms for dependent task(s) with TPOC
### Flaw found after HT3
If a component or subsystem receives passing marks on the HT3 report but a Developer finds a hardware problem after receiving the Sayma v2 hardware the following applies. Said Developer shall
- report the problem and work with the Hardware Developer to identify a patch
- budget 24 hours for hardware-flaw related debugging
- apply white wire patches
- budget for two shipments of PCBs back to Hardware Developer for rework
If shipment budget or hardware-flaw budget is exhausted the Developer may
- cancel dependent task(s) and receive payment for up to 50% task cost
- renegotiate contract terms for dependent task(s) with TPOC
Hardware Developer task HT5 depends on deliverables from Software and Gateware Developer and Integration and Timing Developer. Two provisions are forseen to account for slow or failed delivery of dependencies by other Developers.
- If critical dependencies for HT5 are delayed beyond April 20, the scope of work for HT5 can be renegotiated with TPOC.
- If other Developers provide notice that HT5 dependencies will not be supplied, Hardware Developer may ship demonstration system to UMD without successful completion of a subset of tests ST1, ST2, ST3 and ST4.
Deterministic phase alignment between DACs on separate Sayma PCBs between power cycles is an important design criterion and should be considered at all stages of design. This implies a) SYSREF is aligned with RTIO clock b) DAC clocks are synchronized to local SYSREF edges.
Phase stability between DACs on separate Sayma PCBs is an important design criterion and should be considered at all stages of the design. This assumes that DAC-FPGA synchronization.
- Test conditions
- SAWG output on all channels on two Sayma boards, 400 MHz continuous RF
- Assume laboratory temperature stability +/- 0.5 C
Low cross talk between adjacent analog channels on same AFE is an important design criterion and should be considered at all stages of the design (particularly layout).
The Hardware Developer is responsible for hardware design and manufacturing. Testing responsibilities of the Hardware Developer are those detailed in HT3.
High-level schematics for all PCBs to include component part numbers, high-level component interconnection, power budget, high-level layout of all PCBs including location of ICs, board-to-board headers, RF shielding, heat sinks, mechanical support and front panel design. Post design files to github and tag. Participate in design review on github.
HT1 delivery is complete when the Software and Gateware Developer, Integration and Timing Developer and UMD/ARL sign off on the drawings.
Detailed schematics for all PCBs, finished component interconnections, signal integrity analysis, thermal analysis, power analysis, final PCB routing. Post design files to github and tag. Participate in final design review, accept delegated responsibilities from Software and Gateware Developer Design. Output is layout ready for manufacture.
Hardware Developer shall lead HT2 design review. This design review is in collaboration with scientists and other developers. The review will not be comprehensive. It will focus on differences between v1 and v2 of the hardware. Shall include validation of FPGA pinout.
- Signal integrity testing using any suitable IP (eg Xilinx) for all ICs. Tested individually.
- Design and implement test to simulate heavy loading of a system configured as TS2. The test is expected to simultaneously exercise the following subsystems
- I2C, SPI, address all ICs round robin at full speed
- 2 TestMod installed dissipating representative power
- AD built-in DAC JESD PRBS test at 10 Gb/s lane for both DACs
- SDRAM PRBS write-then-read at [TODO ____ data rate]
- The Hardware Developer retains the following for testing and as backups in case of system integrator hardware failure: 2 AMC, 2 RTM, 4 AFE, 1 Metlino
HT3 delivery is complete when the Software and Gateware Developer and Integration and Timing Developer confirm receipt of hardware.
## __HT4__ documentation and MMC
- Support system integrators by github Issue system.
- If bug fixes are substantial (eg replacing multi-pin SMD), system integrators may at their option return boards to the Hardware Developer for repair. System integrator pays shipping inbound, Hardware Developer pays shipping outbound. Limit to 10 shipping round trips.
- Each board should have a serial number, and a wiki page where everyone who reworks the board has to document what they did. Other notes about that particular board and its specific bugs can be added there.
- MMC and Exar configuration
- Publish source on github within sinara-hw domain.
- Explicit instructions for building and flashing.
- Mimic ARTIQ release structure: tag official releases, change log.
- Formal hardware documentation maintained in github
- Follow ARTIQ model using Sphinx.
- Setup automatic rendering on readthedocs with webhook to git pushes.
- Embed link in github that links to readthedocs.
- scope: expected content is superset of existing Sayma v1 documentation
- scope: documentation to also include the following github Issues
Build demonstration system that is fully assembled and tested. Collect code and test results from other Developers for ST1 to ST4. Reproduce test results on Hardware Developer's system. Add test results to Sayma v2 documentation. The system shall consist of the following components.
HT5 delivery is complete when UMD confirms receipt of the demonstration system /and/ TPOC successfully runs test code. TPOC has 7 business days to conduct tests.
## __HT6__ round up
- Update schematics and layout to remedy bugs.
- Publish to github list of factory acceptance tests including expected results and failure criteria.
Dependency: Software and Gateware Developer is responsible for supplying AD9154 support at the level of M3.04 and M3.06. Integration and Timing Developer will handle debugging of ADF4356 and AD9154 as relates to ST4.
- __O1.04_ based on O1.01, ensure passage of ST3 for a pair of AD9154 DACs on a single Sayma v2 board in configuration TS1. Note that this test is short of the full ST3 test which specifies a pair of Sayma v2 boards.
OT1 delivery is complete when the Integration and Timing Developer completes and documents the above tasks and returns 1 Metlino, 1 Sayma AMC, 1 Sayma RTM, 2 Basemods to the Hardware Developer.
The Software and Gateware Developer is responsible for gateware and software needed to provide ARTIQ support and to implement SAWG. All software and gateware development items include:
- Test benches or unit tests for gateware and software
- __M2.01__ Develop fixed test pattern generator (12-point cosine on odd channels and ramps with major carry toggles on even channels) as a compile time alternative to SAWG.
- __M2.02__ Review and verify Sayma v2 design from the FPGA perspective. Do this by building a stub ARTIQ target and test compilation -- depends on obtaining netlist for FPGAs from Hardware Developer (HT2). This will verify IO assignments and usage patterns around the following subsystems to the level currently used in ARTIQ
- __M3.01__ Review the code emerging from O14 and O15. Support merge into ARTIQ. Aspects included in review: DRTIO-on-RTM, DRTIO clock recovery on RTM, JESD204B deterministic latency/synchronization and DDMTD.
- __M3.02__ Work with TPOC to develop test cases for SAWG v2.0 with ST1 and ST2 in mind. Split into manual test cases and tests amendable to continuous integration (CI). Procure hardware needed for hardware-in-the-loop tests.
- __M3.06__ Validate RF output using SAWG v1.0. This tests operation of SAWG as developed for Sayma v1 works on Sayma v2. It tests the following elements.
Use github Issue tracking for test results and bug tracking. Link back to the old sinara-hw/sinara Issues as needed but don’t conduct new discussions in sinara-hw/sinara.
Weekly discussions via google hangout during period of performance. Attendance of at least one team member for each Developer team is expected. Discussion limited to 30 minutes per week. UMD/ARL involvement if requested by MC.
Master of Ceremonies (MC) expectations:
- Solicit agenda items from group. Select agenda topics that can be completed in 30 minutes.
- Regulate discussion so that planned agenda items are covered. For technical matters that prove contentious or detailed, shift discussion to github Issue.
- Publish agenda > 4 hours prior to meeting start.
- Launch google hangout > 5 minutes in advance of meeting start.
- Schedule next meeting time using doodle; advertise meeting time in UTC
- Each week rotate responsibilities for MC and minutes-taking between Developers and UMD/ARL
Agenda items must include:
- vote on acceptance of last meeting's minutes
- designate next meeting's MC
- designate next meeting minutes-taker
- ask participants to reflect on how the meeting went and what to do better next week