78 lines
2.7 KiB
Python
Executable File
78 lines
2.7 KiB
Python
Executable File
#!/usr/bin/env python
|
|
|
|
import argparse
|
|
from operator import itemgetter
|
|
|
|
from migen import *
|
|
from migen.build.generic_platform import *
|
|
from migen.genlib.cdc import AsyncResetSynchronizer
|
|
from migen_axi.integration.soc_core import SoCCore
|
|
from migen_axi.platforms import redpitaya
|
|
from misoc.integration import cpu_interface
|
|
|
|
import dma
|
|
|
|
|
|
class RustPitaya(SoCCore):
|
|
def __init__(self):
|
|
platform = redpitaya.Platform()
|
|
platform.toolchain.bitstream_commands.extend([
|
|
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
|
|
])
|
|
ident = self.__class__.__name__
|
|
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
|
|
|
|
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
|
|
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
|
|
|
|
# ADC clocking
|
|
clk125_pads = platform.request("clk125")
|
|
platform.add_platform_command("create_clock -name clk_adc -period 8 [get_ports {port}]", port=clk125_pads.p)
|
|
self.clock_domains.cd_adc = ClockDomain()
|
|
self.specials += [
|
|
Instance("IBUFGDS", i_I=clk125_pads.p, i_IB=clk125_pads.n,
|
|
o_O=self.cd_adc.clk),
|
|
AsyncResetSynchronizer(self.cd_adc, ResetSignal()),
|
|
]
|
|
adc_pads = platform.request("adc")
|
|
self.specials += [
|
|
Instance("ODDR", o_Q=adc_pads.clk[0], i_D1=1, i_D2=0, i_CE=1, i_C=self.cd_adc.clk),
|
|
Instance("ODDR", o_Q=adc_pads.clk[1], i_D1=0, i_D2=1, i_CE=1, i_C=self.cd_adc.clk),
|
|
]
|
|
self.comb += adc_pads.cdcs.eq(1)
|
|
for port in adc_pads.data_a, adc_pads.data_b:
|
|
platform.add_platform_command("set_input_delay -max 3.400 -clock clk_adc [get_ports {port}[*]]", port=port)
|
|
|
|
# ADC DMA
|
|
self.submodules.adc = dma.ADC(self.ps7.s_axi_hp0, adc_pads)
|
|
self.csr_devices.append("adc")
|
|
|
|
|
|
def write_csr_file(soc, filename):
|
|
with open(filename, "w") as f:
|
|
f.write(cpu_interface.get_csr_rust(
|
|
soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
|
|
|
|
|
|
|
|
def main():
|
|
parser = argparse.ArgumentParser(
|
|
description="Rust Pitaya gateware")
|
|
parser.add_argument("-r", default=None, metavar="FILE",
|
|
help="build Rust interface into the specified file")
|
|
parser.add_argument("-g", default=None, metavar="DIRECTORY",
|
|
help="build gateware into the specified directory")
|
|
args = parser.parse_args()
|
|
|
|
soc = RustPitaya()
|
|
soc.finalize()
|
|
|
|
if args.r is not None:
|
|
write_csr_file(soc, args.r)
|
|
if args.g is not None:
|
|
soc.build(build_dir=args.g)
|
|
|
|
|
|
if __name__ == "__main__":
|
|
main()
|