86 lines
2.0 KiB
Rust
86 lines
2.0 KiB
Rust
#![no_std]
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#![no_main]
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extern crate alloc;
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use core::{cmp, str};
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use log::{info, warn};
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use libcortex_a9::asm;
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use libboard_zynq::{timer::GlobalTimer, slcr};
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use libsupport_zynq::ram;
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use libconfig::Config;
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use libregister::RegisterW;
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#[path = "../../../build/pl.rs"]
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mod pl;
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fn init_gateware() {
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// Set up PS->PL clocks
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slcr::RegisterBlock::unlocked(|slcr| {
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// As we are touching the mux, the clock may glitch, so reset the PL.
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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.fpga0_out_rst(true)
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.fpga1_out_rst(true)
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.fpga2_out_rst(true)
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.fpga3_out_rst(true)
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);
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slcr.fpga0_clk_ctrl.write(
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slcr::Fpga0ClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor0(8)
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.divisor1(1)
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);
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slcr.fpga_rst_ctrl.write(
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slcr::FpgaRstCtrl::zeroed()
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);
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});
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}
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fn identifier_read(buf: &mut [u8]) -> &str {
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unsafe {
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pl::csr::identifier::address_write(0);
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let len = pl::csr::identifier::data_read();
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let len = cmp::min(len, buf.len() as u8);
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for i in 0..len {
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pl::csr::identifier::address_write(1 + i);
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buf[i as usize] = pl::csr::identifier::data_read();
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}
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str::from_utf8_unchecked(&buf[..len as usize])
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}
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}
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#[no_mangle]
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pub fn main_core0() {
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let mut timer = GlobalTimer::start();
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log::set_max_level(log::LevelFilter::Info);
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info!("Rust Pitaya firmware starting...");
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ram::init_alloc_core0();
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init_gateware();
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info!("detected gateware: {}", identifier_read(&mut [0; 64]));
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let cfg = match Config::new() {
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Ok(cfg) => cfg,
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Err(err) => {
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warn!("config initialization failed: {}", err);
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Config::new_dummy()
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}
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};
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loop {
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asm::wfe();
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}
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}
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#[no_mangle]
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pub fn main_core1() {
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loop {
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asm::wfe();
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}
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}
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