dma: fix/improve logic

This commit is contained in:
Sebastien Bourdeauducq 2022-08-30 16:39:12 +08:00
parent 39b9563d2e
commit ec417eaf1e
1 changed files with 3 additions and 9 deletions

View File

@ -95,10 +95,10 @@ class ADCWriter(Module):
assert AXI_DATA_WIDTH == len(fifo_inbuf)
remaining = Signal(AXI_ADDRESS_WIDTH - log2_int(AXI_DATA_WIDTH//8)) # in AXI_DATA_WIDTH words
self.sync += [
If(remaining != 0, remaining.eq(remaining - 1)),
If(fifo.we & fifo.writable, remaining.eq(remaining - 1)),
If(self.start, remaining.eq(self.length << log2_int(AXI_BURST_LEN))),
]
self.comb += fifo.we.eq((remaining != 0) & ~fifo_inbuf_sel)
self.comb += fifo.we.eq((remaining != 0) & fifo_inbuf_sel)
self.comb += self.overflow.eq(fifo.we & ~fifo.writable)
@ -123,13 +123,7 @@ class ADCWriter(Module):
)
]
# Busy generation
remaining_sys = Signal(AXI_ADDRESS_WIDTH - log2_int(AXI_DATA_WIDTH//8))
self.sync += [
If(self.start, remaining_sys.eq(self.length << log2_int(AXI_BURST_LEN))),
If(fifo.readable & fifo.re, remaining_sys.eq(remaining_sys - 1))
]
self.comb += self.busy.eq(remaining_sys != 0)
self.comb += self.busy.eq((remaining != 0) | fifo.readable)
class ADC(Module, AutoCSR):