From ec417eaf1ee237dd50b269f8c7316b3a5704cf1d Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 30 Aug 2022 16:39:12 +0800
Subject: [PATCH] dma: fix/improve logic

---
 src/gateware/dma.py | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/src/gateware/dma.py b/src/gateware/dma.py
index 4f04b22..5f5d134 100644
--- a/src/gateware/dma.py
+++ b/src/gateware/dma.py
@@ -95,10 +95,10 @@ class ADCWriter(Module):
         assert AXI_DATA_WIDTH == len(fifo_inbuf)
         remaining = Signal(AXI_ADDRESS_WIDTH - log2_int(AXI_DATA_WIDTH//8)) # in AXI_DATA_WIDTH words
         self.sync += [
-            If(remaining != 0, remaining.eq(remaining - 1)),
+            If(fifo.we & fifo.writable, remaining.eq(remaining - 1)),
             If(self.start, remaining.eq(self.length << log2_int(AXI_BURST_LEN))),
         ]
-        self.comb += fifo.we.eq((remaining != 0) & ~fifo_inbuf_sel)
+        self.comb += fifo.we.eq((remaining != 0) & fifo_inbuf_sel)
 
         self.comb += self.overflow.eq(fifo.we & ~fifo.writable)
 
@@ -123,13 +123,7 @@ class ADCWriter(Module):
             )
         ]
 
-        # Busy generation
-        remaining_sys = Signal(AXI_ADDRESS_WIDTH - log2_int(AXI_DATA_WIDTH//8))
-        self.sync += [
-           If(self.start, remaining_sys.eq(self.length << log2_int(AXI_BURST_LEN))),
-           If(fifo.readable & fifo.re, remaining_sys.eq(remaining_sys - 1))
-        ]
-        self.comb += self.busy.eq(remaining_sys != 0)
+        self.comb += self.busy.eq((remaining != 0) | fifo.readable)
 
 
 class ADC(Module, AutoCSR):