diff --git a/flake.nix b/flake.nix index c8e5e07..7353392 100644 --- a/flake.nix +++ b/flake.nix @@ -12,7 +12,11 @@ rustPlatform = artiq-zynq.inputs.zynq-rs.rustPlatform; in { packages.x86_64-linux = rec { - rust-pitaya-firmware = rustPlatform.buildRustPackage { + migen-axi-nosys = artiqzynqpkgs.migen-axi.overrideAttrs(oa: { + patches = [ ./migen-axi-nosys.patch ]; + }); + + rust-pitaya-firmware = rustPlatform.buildRustPackage { name = "rust-pitaya-firmware"; src = ./src; @@ -25,7 +29,7 @@ nativeBuildInputs = [ pkgs.gnumake - (pkgs.python3.withPackages(ps: [ artiqpkgs.migen artiqzynqpkgs.migen-axi artiqpkgs.misoc ])) + (pkgs.python3.withPackages(ps: [ artiqpkgs.migen migen-axi-nosys artiqpkgs.misoc ])) pkgs.cargo-xbuild pkgs.llvmPackages_9.llvm pkgs.llvmPackages_9.clang-unwrapped @@ -50,7 +54,7 @@ rust-pitaya-gateware = pkgs.runCommand "rust-pitaya-gateware" { nativeBuildInputs = [ - (pkgs.python3.withPackages(ps: [ artiqpkgs.migen artiqzynqpkgs.migen-axi artiqpkgs.misoc ])) + (pkgs.python3.withPackages(ps: [ artiqpkgs.migen migen-axi-nosys artiqpkgs.misoc ])) artiqpkgs.vivado ]; } @@ -105,7 +109,7 @@ pkgs.openocd pkgs.openssh pkgs.rsync - (pkgs.python3.withPackages(ps: [ artiqpkgs.migen artiqzynqpkgs.migen-axi artiqpkgs.misoc artiqzynqpkgs.artiq-netboot ])) + (pkgs.python3.withPackages(ps: [ artiqpkgs.migen self.packages.x86_64-linux.migen-axi-nosys artiqpkgs.misoc artiqzynqpkgs.artiq-netboot ])) artiqpkgs.vivado zynqpkgs.mkbootimage diff --git a/migen-axi-nosys.patch b/migen-axi-nosys.patch new file mode 100644 index 0000000..1efbd33 --- /dev/null +++ b/migen-axi-nosys.patch @@ -0,0 +1,26 @@ +diff --git a/src/migen_axi/cores/ps7.py b/src/migen_axi/cores/ps7.py +index 616b65c..ee56d19 100644 +--- a/src/migen_axi/cores/ps7.py ++++ b/src/migen_axi/cores/ps7.py +@@ -396,9 +396,6 @@ class PS7(Module): + self.ddr_arb = Signal(4) + self.mio = Signal(54) + +- self.clock_domains.cd_sys = ClockDomain() +- self.clock_domains.cd_por = ClockDomain(reset_less=True) +- + self.dma0 = dmac_bus.Interface(name="dma0") + self.dma1 = dmac_bus.Interface(name="dma1") + self.dma2 = dmac_bus.Interface(name="dma2") +@@ -491,11 +488,6 @@ class PS7(Module): + ] + + self.fclk = fclk_rec() +- # fclk.reset_n considered async +- self.specials += [ +- AsyncResetSynchronizer(self.cd_sys, ~self.fclk.reset_n[0]), +- bufg([self.fclk.clk[0], ClockSignal()]), +- ] + + self.comb += self.fclk.clktrig_n.eq(0) + ftmd = ftmd_rec() diff --git a/src/gateware/dma.py b/src/gateware/dma.py index 97afd12..4f04b22 100644 --- a/src/gateware/dma.py +++ b/src/gateware/dma.py @@ -1,7 +1,6 @@ from migen import * from migen.genlib.fsm import FSM -from migen.genlib.fifo import AsyncFIFOBuffered -from migen.genlib.cdc import MultiReg, PulseSynchronizer +from migen.genlib.fifo import SyncFIFOBuffered from migen_axi.interconnect import axi from misoc.interconnect.csr import * @@ -70,22 +69,20 @@ class ADCWriter(Module): self.overflow = Signal() self.busy = Signal() - fifo = ClockDomainsRenamer({"write": "adc", "read": "sys"})(AsyncFIFOBuffered(64, 512)) + fifo = SyncFIFOBuffered(64, 512) self.submodules += fifo # FIFO write adc_a = Signal(16) adc_b = Signal(16) - self.sync.adc += [ - #adc_a.eq(pads.data_a), - #adc_b.eq(pads.data_b), - adc_a.eq(0x7842), - adc_b.eq(0xdf86), + self.sync += [ + adc_a.eq(pads.data_a), + adc_b.eq(pads.data_b), ] fifo_inbuf = Signal(64) fifo_inbuf_sel = Signal() - self.sync.adc += [ + self.sync += [ fifo_inbuf_sel.eq(~fifo_inbuf_sel), If(fifo_inbuf_sel, fifo_inbuf[32:].eq(Cat(adc_a, adc_b)), @@ -95,31 +92,15 @@ class ADCWriter(Module): ] self.comb += fifo.din.eq(fifo_inbuf), - length = Signal(AXI_ALIGNED_ADDRESS_WIDTH) - start = Signal() - assert AXI_DATA_WIDTH == len(fifo_inbuf) remaining = Signal(AXI_ADDRESS_WIDTH - log2_int(AXI_DATA_WIDTH//8)) # in AXI_DATA_WIDTH words - self.sync.adc += [ + self.sync += [ If(remaining != 0, remaining.eq(remaining - 1)), - If(start, remaining.eq(length << log2_int(AXI_BURST_LEN))), + If(self.start, remaining.eq(self.length << log2_int(AXI_BURST_LEN))), ] self.comb += fifo.we.eq((remaining != 0) & ~fifo_inbuf_sel) - overflow = Signal() - self.comb += overflow.eq(fifo.we & ~fifo.writable) - - # control CDC - self.specials += MultiReg(self.length, length, "adc") - ps_start = PulseSynchronizer("sys", "adc") - ps_overflow = PulseSynchronizer("adc", "sys") - self.submodules += ps_start, ps_overflow - self.comb += [ - ps_start.i.eq(self.start), - start.eq(ps_start.o), - ps_overflow.i.eq(overflow), - self.overflow.eq(ps_overflow.o) - ] + self.comb += self.overflow.eq(fifo.we & ~fifo.writable) # FIFO read self.comb += [ diff --git a/src/gateware/rust-pitaya.py b/src/gateware/rust-pitaya.py index b05e8b0..d3cbe05 100755 --- a/src/gateware/rust-pitaya.py +++ b/src/gateware/rust-pitaya.py @@ -22,22 +22,18 @@ class RustPitaya(SoCCore): ident = self.__class__.__name__ SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) - platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]") - platform.add_platform_command("set_input_jitter clk_fpga_0 0.24") - - # ADC clocking + # CLock everything from the ADC clock clk125_pads = platform.request("clk125") - platform.add_platform_command("create_clock -name clk_adc -period 8 [get_ports {port}]", port=clk125_pads.p) - self.clock_domains.cd_adc = ClockDomain() - self.specials += [ + platform.add_platform_command("create_clock -name clk_sys -period 8 [get_ports {port}]", port=clk125_pads.p) + self.clock_domains.cd_sys = ClockDomain(reset_less=True) + self.specials += \ Instance("IBUFGDS", i_I=clk125_pads.p, i_IB=clk125_pads.n, - o_O=self.cd_adc.clk), - AsyncResetSynchronizer(self.cd_adc, ResetSignal()), - ] + o_O=self.cd_sys.clk) + adc_pads = platform.request("adc") self.comb += adc_pads.cdcs.eq(1) for port in adc_pads.data_a, adc_pads.data_b: - platform.add_platform_command("set_input_delay -max 3.400 -clock clk_adc [get_ports {port}[*]]", port=port) + platform.add_platform_command("set_input_delay -max 3.400 -clock clk_sys [get_ports {port}[*]]", port=port) # ADC DMA self.submodules.adc = dma.ADC(self.ps7.s_axi_hp0, adc_pads)