From 77f727e71e68d642eca2440974637bdf920d2d63 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 29 Aug 2022 22:16:03 +0800 Subject: [PATCH] stop driving FCLK --- src/gateware/rust-pitaya.py | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/gateware/rust-pitaya.py b/src/gateware/rust-pitaya.py index 8444e3b..b05e8b0 100755 --- a/src/gateware/rust-pitaya.py +++ b/src/gateware/rust-pitaya.py @@ -35,10 +35,6 @@ class RustPitaya(SoCCore): AsyncResetSynchronizer(self.cd_adc, ResetSignal()), ] adc_pads = platform.request("adc") - self.specials += [ - Instance("ODDR", o_Q=adc_pads.clk[0], i_D1=1, i_D2=0, i_CE=1, i_C=self.cd_adc.clk), - Instance("ODDR", o_Q=adc_pads.clk[1], i_D1=0, i_D2=1, i_CE=1, i_C=self.cd_adc.clk), - ] self.comb += adc_pads.cdcs.eq(1) for port in adc_pads.data_a, adc_pads.data_b: platform.add_platform_command("set_input_delay -max 3.400 -clock clk_adc [get_ports {port}[*]]", port=port)