From 39b9563d2eb285aa9f9e1accbe5e05913cf2c69b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 30 Aug 2022 16:38:41 +0800 Subject: [PATCH] typo --- src/gateware/rust-pitaya.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gateware/rust-pitaya.py b/src/gateware/rust-pitaya.py index d3cbe05..e783331 100755 --- a/src/gateware/rust-pitaya.py +++ b/src/gateware/rust-pitaya.py @@ -22,7 +22,7 @@ class RustPitaya(SoCCore): ident = self.__class__.__name__ SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident) - # CLock everything from the ADC clock + # Clock everything from the ADC clock clk125_pads = platform.request("clk125") platform.add_platform_command("create_clock -name clk_sys -period 8 [get_ports {port}]", port=clk125_pads.p) self.clock_domains.cd_sys = ClockDomain(reset_less=True)