diff --git a/src/gateware/rust-pitaya.py b/src/gateware/rust-pitaya.py
index d3cbe05..e783331 100755
--- a/src/gateware/rust-pitaya.py
+++ b/src/gateware/rust-pitaya.py
@@ -22,7 +22,7 @@ class RustPitaya(SoCCore):
         ident = self.__class__.__name__
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
 
-        # CLock everything from the ADC clock
+        # Clock everything from the ADC clock
         clk125_pads = platform.request("clk125")
         platform.add_platform_command("create_clock -name clk_sys -period 8 [get_ports {port}]", port=clk125_pads.p)
         self.clock_domains.cd_sys = ClockDomain(reset_less=True)