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dma: work around BRAM->AXI Xilinx insanity

This commit is contained in:
Sebastien Bourdeauducq 2022-08-30 16:41:45 +08:00
parent ec417eaf1e
commit 13a44fc185
1 changed files with 2 additions and 2 deletions
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4
src/gateware/dma.py
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@ -1,6 +1,6 @@
from migen import * from migen import *
from migen.genlib.fsm import FSM from migen.genlib.fsm import FSM
from migen.genlib.fifo import SyncFIFOBuffered from migen.genlib.fifo import SyncFIFO
from migen_axi.interconnect import axi from migen_axi.interconnect import axi
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
@ -69,7 +69,7 @@ class ADCWriter(Module):
self.overflow = Signal() self.overflow = Signal()
self.busy = Signal() self.busy = Signal()
fifo = SyncFIFOBuffered(64, 512) fifo = SyncFIFO(64, 32, fwft=True)
self.submodules += fifo self.submodules += fifo
# FIFO write # FIFO write