From 13a44fc18591c605e89db86c74ea804a3ed8a0d8 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 30 Aug 2022 16:41:45 +0800
Subject: [PATCH] dma: work around BRAM->AXI Xilinx insanity

---
 src/gateware/dma.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gateware/dma.py b/src/gateware/dma.py
index 5f5d134..a99bbe3 100644
--- a/src/gateware/dma.py
+++ b/src/gateware/dma.py
@@ -1,6 +1,6 @@
 from migen import *
 from migen.genlib.fsm import FSM
-from migen.genlib.fifo import SyncFIFOBuffered
+from migen.genlib.fifo import SyncFIFO
 from migen_axi.interconnect import axi
 from misoc.interconnect.csr import *
 
@@ -69,7 +69,7 @@ class ADCWriter(Module):
         self.overflow = Signal()
         self.busy = Signal()
 
-        fifo = SyncFIFOBuffered(64, 512)
+        fifo = SyncFIFO(64, 32, fwft=True)
         self.submodules += fifo
 
         # FIFO write