diff --git a/README.md b/README.md
index 37ce389..7c5f4db 100644
--- a/README.md
+++ b/README.md
@@ -6,7 +6,7 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen
 
 - Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen
 - [x] Implement the core in nMigen
-- - [ ] `rtio.cri` (`Interface` and `CRIDecoder` only)
+- - [x] `rtio.cri` (`Interface` and `CRIDecoder` only)
 - - [x] `rtio.rtlink`
 - - [x] `rtio.sed.layouts`
 - - [x] `rtio.sed.output_network`
diff --git a/rtio/cri.py b/rtio/cri.py
index 0c2cad7..2dcbdef 100644
--- a/rtio/cri.py
+++ b/rtio/cri.py
@@ -89,7 +89,7 @@ class CRIDecoder(Elaboratable):
             if mode == "async":
                 rtp_decoder = routing_table.read_port()
             elif mode == "sync":
-                rtp_decoder = routing_table.read_port(clock_domain="rtio") # FIXME
+                rtp_decoder = routing_table.read_port(domain="rtio")
             else:
                 raise ValueError
             m.submodules += rtp_decoder