Add failing trace and trace analysis

README.md

@@ -2,6 +2,14 @@
 
 Formally verified implementation of the ARTIQ RTIO core in nMigen
 
+## File Synopsis
+
+- `LICENSE`: License terms (LGPLv3+) for this project
+- `README.md`: this document
+- `shell.nix`: Nix file for setting up the environment for this project
+- `rtio`: RTIO core in nMigen
+- `traces`: History of traces for debugging
+
 ## Progress
 
 - Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen

rtio/sed/output_network.py

@@ -119,16 +119,7 @@ class OutputNetwork(Elaboratable):
             f_past_valid = Signal()
             m.d.sync += f_past_valid.eq(1)
 
-            # Skip assertions for the first 10 time steps
-            counter = Signal(4)
-            m.d.sync += counter.eq(counter + 1)
-            with m.If(counter >= 10):
-                m.d.sync += counter.eq(counter)
-            f_past10_valid = Signal()
-            m.d.comb += f_past10_valid.eq(counter >= 10)
-
             # Valid nodes always come first in outputs
-            with m.If(f_past10_valid):
             for i in range(lane_count - 1):
                 m.d.comb += Assert(self.output[i].valid | ~self.output[i + 1].valid) # TODO: Figure out why this is failing
 

traces/0/NOTES.md

@@ -0,0 +1,92 @@
+# Dissecting the failing trace
+
+N.B. The value of a node `n` is given by `Cat(n.payload.channel, ~n.valid)`
+
+## Cycle \#0 (MATCH)
+
+Events: N/A
+
+Values:
+
+- node0 value: `0010`
+  - node0 valid: `1`
+  - node0 channel: `010`
+  - node0 sequence: `00`
+- node1 value: `0000`
+  - node1 valid: `1`
+  - node1 channel: `000`
+  - node1 sequence: `00`
+- node2 value: `0001`
+  - node2 valid: `1`
+  - node2 channel: `001`
+  - node2 sequence: `11`
+- node3 value: `0000`
+  - node3 valid: `1`
+  - node3 channel: `000`
+  - node3 sequence: `01`
+
+To compare:
+
+- node0 and node1
+- node2 and node3
+
+## Cycle \#1 (MATCH)
+
+Events: N/A
+
+Values:
+
+- node0 value: `0000`
+  - node0 valid: `1`
+  - node0 channel: `000`
+  - node0 sequence: `00`
+- node1 value: `0010`
+  - node1 valid: `1`
+  - node1 channel: `010`
+  - node1 sequence: `00`
+- node2 value: `0000`
+  - node2 valid: `1`
+  - node2 channel: `000`
+  - node2 sequence: `01`
+- node3 value: `0001`
+  - node3 valid: `1`
+  - node3 channel: `001`
+  - node3 sequence: `11`
+
+To compare:
+
+- node0 and node2
+- node1 and node3
+
+## Cycle \#2 (NOMATCH - see trace for diff)
+
+Events:
+
+- A replacement occurred when comparing node0 and node2
+
+Values:
+
+- node0 value: `0000`
+  - node0 valid: `1`
+  - node0 channel: `000`
+  - node0 sequence: `01`
+- node1 value: `0001`
+  - node1 valid: `1`
+  - node1 channel: `001`
+  - node1 sequence: `11`
+- node2 value: `1000`
+  - node2 valid: `0`
+  - node2 channel: `000`
+  - node2 sequence: `00`
+- node3 value: `0010`
+  - node3 valid: `1`
+  - node3 channel: `010`
+  - node3 sequence: `00`
+
+To compare:
+
+- node1 and node2
+
+# Cycle \#3
+
+TODO: fill this in after figuring out why my prediction for Cycle \#2 fails to match generated trace

traces/0/trace.vcd

@@ -0,0 +1,786 @@
+$version Generated by Yosys-SMTBMC $end
+$timescale 1ns $end
+$var integer 32 t smt_step $end
+$var event 1 ! smt_clock $end
+$scope module top $end
+$var wire 1 n0 clk $end
+$var wire 1 n1 f_past_valid $end
+$var wire 1 n2 nondata_difference $end
+$var wire 1 n3 nondata_difference$127 $end
+$var wire 1 n4 nondata_replace_occured $end
+$var wire 1 n5 nondata_replace_occured$22 $end
+$var wire 1 n6 nondata_replace_occured$40 $end
+$var wire 1 n7 nondata_replace_occured$58 $end
+$var wire 3 n8 payload__channel $end
+$var wire 3 n9 payload__channel$28 $end
+$var wire 3 n10 payload__channel$46 $end
+$var wire 3 n11 payload__channel$64 $end
+$var wire 32 n12 payload__data $end
+$var wire 32 n13 payload__data$25 $end
+$var wire 32 n14 payload__data$43 $end
+$var wire 32 n15 payload__data$61 $end
+$var wire 1 n16 rec__nondata_replace_occured $end
+$var wire 1 n17 rec__nondata_replace_occured$133 $end
+$var wire 1 n18 rec__nondata_replace_occured$133$next $end
+$var wire 1 n19 rec__nondata_replace_occured$165 $end
+$var wire 1 n20 rec__nondata_replace_occured$165$next $end
+$var wire 1 n21 rec__nondata_replace_occured$200 $end
+$var wire 1 n22 rec__nondata_replace_occured$232 $end
+$var wire 1 n23 rec__nondata_replace_occured$232$next $end
+$var wire 1 n24 rec__nondata_replace_occured$267 $end
+$var wire 1 n25 rec__nondata_replace_occured$299 $end
+$var wire 1 n26 rec__nondata_replace_occured$334 $end
+$var wire 1 n27 rec__nondata_replace_occured$366 $end
+$var wire 1 n28 rec__nondata_replace_occured$398 $end
+$var wire 1 n29 rec__nondata_replace_occured$398$next $end
+$var wire 1 n30 rec__nondata_replace_occured$404 $end
+$var wire 1 n31 rec__nondata_replace_occured$404$next $end
+$var wire 1 n32 rec__nondata_replace_occured$98 $end
+$var wire 1 n33 rec__nondata_replace_occured$98$next $end
+$var wire 1 n34 rec__nondata_replace_occured$next $end
+$var wire 3 n35 rec__payload__channel $end
+$var wire 3 n36 rec__payload__channel$100 $end
+$var wire 3 n37 rec__payload__channel$100$next $end
+$var wire 3 n38 rec__payload__channel$135 $end
+$var wire 3 n39 rec__payload__channel$135$next $end
+$var wire 3 n40 rec__payload__channel$167 $end
+$var wire 3 n41 rec__payload__channel$167$next $end
+$var wire 3 n42 rec__payload__channel$202 $end
+$var wire 3 n43 rec__payload__channel$234 $end
+$var wire 3 n44 rec__payload__channel$234$next $end
+$var wire 3 n45 rec__payload__channel$269 $end
+$var wire 3 n46 rec__payload__channel$269$next $end
+$var wire 3 n47 rec__payload__channel$301 $end
+$var wire 3 n48 rec__payload__channel$336 $end
+$var wire 3 n49 rec__payload__channel$368 $end
+$var wire 3 n50 rec__payload__channel$400 $end
+$var wire 3 n51 rec__payload__channel$400$next $end
+$var wire 3 n52 rec__payload__channel$406 $end
+$var wire 3 n53 rec__payload__channel$406$next $end
+$var wire 3 n54 rec__payload__channel$next $end
+$var wire 32 n55 rec__payload__data $end
+$var wire 32 n56 rec__payload__data$134 $end
+$var wire 32 n57 rec__payload__data$134$next $end
+$var wire 32 n58 rec__payload__data$166 $end
+$var wire 32 n59 rec__payload__data$166$next $end
+$var wire 32 n60 rec__payload__data$201 $end
+$var wire 32 n61 rec__payload__data$233 $end
+$var wire 32 n62 rec__payload__data$233$next $end
+$var wire 32 n63 rec__payload__data$268 $end
+$var wire 32 n64 rec__payload__data$268$next $end
+$var wire 32 n65 rec__payload__data$300 $end
+$var wire 32 n66 rec__payload__data$335 $end
+$var wire 32 n67 rec__payload__data$367 $end
+$var wire 32 n68 rec__payload__data$399 $end
+$var wire 32 n69 rec__payload__data$399$next $end
+$var wire 32 n70 rec__payload__data$405 $end
+$var wire 32 n71 rec__payload__data$405$next $end
+$var wire 32 n72 rec__payload__data$99 $end
+$var wire 32 n73 rec__payload__data$99$next $end
+$var wire 32 n74 rec__payload__data$next $end
+$var wire 1 n75 rec__replace_occured $end
+$var wire 1 n76 rec__replace_occured$132 $end
+$var wire 1 n77 rec__replace_occured$132$next $end
+$var wire 1 n78 rec__replace_occured$164 $end
+$var wire 1 n79 rec__replace_occured$164$next $end
+$var wire 1 n80 rec__replace_occured$199 $end
+$var wire 1 n81 rec__replace_occured$231 $end
+$var wire 1 n82 rec__replace_occured$231$next $end
+$var wire 1 n83 rec__replace_occured$266 $end
+$var wire 1 n84 rec__replace_occured$298 $end
+$var wire 1 n85 rec__replace_occured$333 $end
+$var wire 1 n86 rec__replace_occured$365 $end
+$var wire 1 n87 rec__replace_occured$397 $end
+$var wire 1 n88 rec__replace_occured$397$next $end
+$var wire 1 n89 rec__replace_occured$403 $end
+$var wire 1 n90 rec__replace_occured$403$next $end
+$var wire 1 n91 rec__replace_occured$97 $end
+$var wire 1 n92 rec__replace_occured$97$next $end
+$var wire 1 n93 rec__replace_occured$next $end
+$var wire 2 n94 rec__seqn $end
+$var wire 2 n95 rec__seqn$131 $end
+$var wire 2 n96 rec__seqn$131$next $end
+$var wire 2 n97 rec__seqn$163 $end
+$var wire 2 n98 rec__seqn$163$next $end
+$var wire 2 n99 rec__seqn$198 $end
+$var wire 2 n100 rec__seqn$230 $end
+$var wire 2 n101 rec__seqn$230$next $end
+$var wire 2 n102 rec__seqn$265 $end
+$var wire 2 n103 rec__seqn$265$next $end
+$var wire 2 n104 rec__seqn$297 $end
+$var wire 2 n105 rec__seqn$332 $end
+$var wire 2 n106 rec__seqn$364 $end
+$var wire 2 n107 rec__seqn$396 $end
+$var wire 2 n108 rec__seqn$396$next $end
+$var wire 2 n109 rec__seqn$402 $end
+$var wire 2 n110 rec__seqn$402$next $end
+$var wire 2 n111 rec__seqn$96 $end
+$var wire 2 n112 rec__seqn$96$next $end
+$var wire 2 n113 rec__seqn$next $end
+$var wire 1 n114 rec__valid $end
+$var wire 1 n115 rec__valid$130 $end
+$var wire 1 n116 rec__valid$130$next $end
+$var wire 1 n117 rec__valid$162 $end
+$var wire 1 n118 rec__valid$162$next $end
+$var wire 1 n119 rec__valid$197 $end
+$var wire 1 n120 rec__valid$197$next $end
+$var wire 1 n121 rec__valid$229 $end
+$var wire 1 n122 rec__valid$229$next $end
+$var wire 1 n123 rec__valid$264 $end
+$var wire 1 n124 rec__valid$264$next $end
+$var wire 1 n125 rec__valid$296 $end
+$var wire 1 n126 rec__valid$296$next $end
+$var wire 1 n127 rec__valid$331 $end
+$var wire 1 n128 rec__valid$331$next $end
+$var wire 1 n129 rec__valid$363 $end
+$var wire 1 n130 rec__valid$363$next $end
+$var wire 1 n131 rec__valid$395 $end
+$var wire 1 n132 rec__valid$395$next $end
+$var wire 1 n133 rec__valid$401 $end
+$var wire 1 n134 rec__valid$401$next $end
+$var wire 1 n135 rec__valid$95 $end
+$var wire 1 n136 rec__valid$95$next $end
+$var wire 1 n137 rec__valid$next $end
+$var wire 1 n138 replace_occured $end
+$var wire 1 n139 replace_occured$19 $end
+$var wire 1 n140 replace_occured$37 $end
+$var wire 1 n141 replace_occured$55 $end
+$var wire 1 n142 rst $end
+$var wire 2 n143 seqn $end
+$var wire 2 n144 seqn$16 $end
+$var wire 2 n145 seqn$34 $end
+$var wire 2 n146 seqn$52 $end
+$var wire 1 n147 valid $end
+$var wire 1 n148 valid$13 $end
+$var wire 1 n149 valid$31 $end
+$var wire 1 n150 valid$49 $end
+$upscope $end
+$enddefinitions $end
+#0
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+1!
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