Remove assertions involving invalid inputs
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2d801d1aef
commit
96e7a79502
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@ -35,10 +35,10 @@ class OutputNetworkSpec(Elaboratable):
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m.d.comb += f_output_valid.eq(counter == network_latency)
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with m.If(f_output_valid):
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replacement_occurred = Signal()
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valid_replacement_occurred = Signal()
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for node in output_network.output:
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with m.If(node.replace_occured):
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m.d.comb += replacement_occurred.eq(1)
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with m.If(node.valid & node.replace_occured):
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m.d.comb += valid_replacement_occurred.eq(1)
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valid_channels_unique = Signal(reset=1)
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for node1 in range(len(output_network.input)):
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with m.If(Past(output_network.input[node1].valid, clocks=network_latency)):
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@ -48,21 +48,11 @@ class OutputNetworkSpec(Elaboratable):
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k2 = Past(output_network.input[node2].payload.channel, clocks=network_latency)
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with m.If(k1 == k2):
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m.d.comb += valid_channels_unique.eq(0)
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invalid_channels_unique = Signal(reset=1)
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for node1 in range(len(output_network.input)):
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with m.If(~Past(output_network.input[node1].valid, clocks=network_latency)):
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for node2 in range(node1):
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with m.If(~Past(output_network.input[node2].valid, clocks=network_latency)):
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k1 = Past(output_network.input[node1].payload.channel, clocks=network_latency)
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k2 = Past(output_network.input[node2].payload.channel, clocks=network_latency)
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with m.If(k1 == k2):
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m.d.comb += invalid_channels_unique.eq(0)
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# If there are no replacements then:
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# - Input channel numbers are unique among (in)valid nodes
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# - All inputs make it through the sorting network unmodified
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with m.If(~replacement_occurred):
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# Among the valid outputs, if there are no replacements then:
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# - Channel numbers are unique among valid inputs
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# - All valid inputs make it through the sorting network unmodified
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with m.If(~valid_replacement_occurred):
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m.d.comb += Assert(valid_channels_unique)
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m.d.comb += Assert(invalid_channels_unique)
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for input_node in output_network.input:
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appeared = Signal()
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for output_node in output_network.output:
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@ -80,18 +70,16 @@ class OutputNetworkSpec(Elaboratable):
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m.d.comb += match.eq(0)
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with m.If(match):
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m.d.comb += appeared.eq(1)
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m.d.comb += Assert(appeared)
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# Otherwise, if there are replacements:
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# - There is a channel number collision among the valid or invalid
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# nodes
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with m.If(Past(input_node.valid, clocks=network_latency)):
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m.d.comb += Assert(appeared)
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# Otherwise:
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# - There is a channel number collision among the valid inputs
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# - All channel numbers in valid inputs appear exactly once as a
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# valid output
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# - All valid outputs correspond to a valid input modulo accounting
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# information
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# - Channel numbers in invalid inputs not appearing in valid inputs
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# as well never appear as a valid output
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with m.Else():
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m.d.comb += Assert(~valid_channels_unique | ~invalid_channels_unique)
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m.d.comb += Assert(~valid_channels_unique)
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for input_node in output_network.input:
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input_channel_valid_once = Const(0)
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for node1 in range(len(output_network.output)):
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@ -117,18 +105,6 @@ class OutputNetworkSpec(Elaboratable):
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with m.If(match):
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m.d.comb += found_input.eq(1)
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m.d.comb += Assert(found_input)
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for node1 in output_network.input:
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with m.If(~Past(node1.valid, clocks=network_latency)):
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has_valid_input = Signal()
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for node2 in output_network.input:
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with m.If(Past(node2.valid, clocks=network_latency) & (Past(node1.payload.channel, clocks=network_latency) == Past(node2.payload.channel, clocks=network_latency))):
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m.d.comb += has_valid_input.eq(1)
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with m.If(~has_valid_input):
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has_valid_output = Signal()
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for output_node in output_network.output:
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with m.If(output_node.valid & (output_node.payload.channel == Past(node1.payload.channel, clocks=network_latency))):
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m.d.comb += has_valid_output.eq(1)
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m.d.comb += Assert(~has_valid_output)
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return m
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