From 96d470921b9295c12dd0fd5ddb0cf4d950948625 Mon Sep 17 00:00:00 2001
From: Donald Sebastian Leung <dl@m-labs.hk>
Date: Wed, 21 Oct 2020 14:03:35 +0800
Subject: [PATCH] Fix assertions for no replacements case

---
 rtio/sed/output_network.py | 37 ++++++++++++++++++-------------------
 1 file changed, 18 insertions(+), 19 deletions(-)

diff --git a/rtio/sed/output_network.py b/rtio/sed/output_network.py
index 25fdeca..22f9238 100644
--- a/rtio/sed/output_network.py
+++ b/rtio/sed/output_network.py
@@ -145,25 +145,24 @@ class OutputNetwork(Elaboratable):
                             with m.If(k1 == k2):
                                 m.d.comb += nodes_unique.eq(0)
                     m.d.comb += Assert(nodes_unique)
-                    # TODO: figure out why the rest is failing
-                    # appeared = Signal(len(self.input))
-                    # for input_node in range(len(self.input)):
-                        # for output_node in self.output:
-                            # identical = Signal(reset=1)
-                            # with m.If(Past(self.input[input_node].valid, clocks=network_latency) != output_node.valid):
-                                # m.d.comb += identical.eq(0)
-                            # with m.If(Past(self.input[input_node].seqn, clocks=network_latency) != output_node.seqn):
-                                # m.d.comb += identical.eq(0)
-                            # with m.If(Past(self.input[input_node].replace_occured, clocks=network_latency) != output_node.replace_occured):
-                                # m.d.comb += identical.eq(0)
-                            # with m.If(Past(self.input[input_node].nondata_replace_occured, clocks=network_latency) != output_node.nondata_replace_occured):
-                                # m.d.comb += identical.eq(0)
-                            # for field, _ in layout_payload:
-                                # with m.If(Past(getattr(self.input[input_node].payload, field), clocks=network_latency) != getattr(output_node.payload, field)):
-                                    # m.d.comb += identical.eq(0)
-                            # m.d.comb += appeared[input_node].eq(identical)
-                    # for i in range(len(self.input)):
-                        # m.d.comb += Assert(appeared[i])
+                    for input_node in self.input:
+                        appeared = Signal()
+                        for output_node in self.output:
+                            match = Signal(reset=1)
+                            with m.If(Past(input_node.valid, clocks=network_latency) != output_node.valid):
+                                m.d.comb += match.eq(0)
+                            with m.If(Past(input_node.seqn, clocks=network_latency) != output_node.seqn):
+                                m.d.comb += match.eq(0)
+                            with m.If(Past(input_node.replace_occured, clocks=network_latency) != output_node.replace_occured):
+                                m.d.comb += match.eq(0)
+                            with m.If(Past(input_node.nondata_replace_occured, clocks=network_latency) != output_node.nondata_replace_occured):
+                                m.d.comb += match.eq(0)
+                            for field, _ in layout_payload:
+                                with m.If(Past(getattr(input_node.payload, field), clocks=network_latency) != getattr(output_node.payload, field)):
+                                    m.d.comb += match.eq(0)
+                            with m.If(match):
+                                m.d.comb += appeared.eq(1)
+                        m.d.comb += Assert(appeared)
 
             # If the valid bit / channel no. combinations of all input data are
             # unique then there should be no replacements