Remove redundant 'artiq.gateware' from module names

This commit is contained in:
Donald Sebastian Leung 2020-09-25 15:10:07 +08:00
parent a788c17e3d
commit 1a83778590
20 changed files with 14 additions and 15 deletions

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@ -5,19 +5,18 @@ Formally verified implementation of the ARTIQ RTIO core in nMigen
## Progress ## Progress
- [ ] Implement the core in nMigen - [ ] Implement the core in nMigen
- - [ ] `artiq.gateware.rtio.core` - - [ ] `rtio.core`
- - [ ] `misoc.interconnect.csr` - - [ ] `rtio.cri`
- - [ ] `artiq.gateware.rtio.cri` - - [x] `rtio.rtlink`
- - [x] `artiq.gateware.rtio.rtlink` - - [x] `rtio.channel`
- - [x] `artiq.gateware.rtio.channel` - - [ ] `rtio.sed.core`
- - [ ] `artiq.gateware.rtio.sed.core` - - [x] `rtio.sed.layouts`
- - [x] `artiq.gateware.rtio.sed.layouts` - - [ ] `rtio.sed.lane_distributor`
- - [ ] `artiq.gateware.rtio.sed.lane_distributor` - - [ ] `rtio.sed.fifos`
- - [ ] `artiq.gateware.rtio.sed.fifos` - - [ ] `rtio.sed.gates`
- - [ ] `artiq.gateware.rtio.sed.gates` - - [ ] `rtio.sed.output_driver`
- - [ ] `artiq.gateware.rtio.sed.output_driver` - - [ ] `rtio.sed.output_network`
- - [ ] `artiq.gateware.rtio.sed.output_network` - - [ ] `rtio.input_collector`
- - [ ] `artiq.gateware.rtio.input_collector`
- [ ] Add suitable assertions for verification (BMC / unbounded proof?) - [ ] Add suitable assertions for verification (BMC / unbounded proof?)
## License ## License

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@ -1,6 +1,6 @@
import warnings import warnings
from artiq.gateware.rtio import rtlink from rtio import rtlink
class Channel: class Channel:

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@ -2,7 +2,7 @@ from nmigen import *
from nmigen.utils import * from nmigen.utils import *
from nmigen.hdl.rec import * from nmigen.hdl.rec import *
from artiq.gateware.rtio import rtlink from rtio import rtlink
def fifo_payload(channels): def fifo_payload(channels):