2020-09-23 17:10:41 +08:00
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# rtio-nmigen
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2020-09-23 17:14:27 +08:00
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Formally verified implementation of the ARTIQ RTIO core in nMigen
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2020-10-20 13:05:38 +08:00
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## File Synopsis
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- `LICENSE`: License terms (LGPLv3+) for this project
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- `README.md`: this document
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- `shell.nix`: Nix file for setting up the environment for this project
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- `rtio`: RTIO core in nMigen
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- `traces`: History of traces for debugging
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2020-09-23 17:14:27 +08:00
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## Progress
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2020-09-30 10:55:08 +08:00
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- Devise a suitable migration strategy for `artiq.gateware.rtio` from Migen to nMigen
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2020-10-09 11:16:01 +08:00
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- [x] Implement the core in nMigen
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2020-10-15 13:11:06 +08:00
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- - [x] `rtio.cri` (`Interface` and `CRIDecoder` only)
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2020-10-07 16:32:20 +08:00
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- - [x] `rtio.rtlink`
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2020-10-08 11:06:35 +08:00
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- - [x] `rtio.sed.layouts`
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2020-10-08 17:05:04 +08:00
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- - [x] `rtio.sed.output_network`
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2020-10-09 11:16:01 +08:00
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- - [x] `rtio.sed.output_driver`
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2020-09-23 17:14:27 +08:00
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- [ ] Add suitable assertions for verification (BMC / unbounded proof?)
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2020-10-14 16:50:01 +08:00
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- - [ ] `rtio.cri` (`Interface` and `CRIDecoder` only)
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- - [ ] `rtio.rtlink`
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- - [ ] `rtio.sed.layouts`
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- - [ ] `rtio.sed.output_network` - Sorting network (high priority)
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2020-10-14 16:50:57 +08:00
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- - [ ] `rtio.sed.output_driver`
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2020-10-19 14:42:38 +08:00
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- [ ] Restructure to code to follow nMigen convention and re-validate existing assertions
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2020-09-23 17:14:27 +08:00
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## License
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Copyright (C) 2020 M-Labs Limited.
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2020-09-23 17:16:58 +08:00
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[LGPLv3](./LICENSE) or any later version
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