46 lines
1.0 KiB
Python
46 lines
1.0 KiB
Python
from nmigen import *
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"""
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Instruction Bus (Wishbone Slave)
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"""
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# TODO: Perhaps axiomatize a read-only instruction store where the
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# instruction bus reads from when requested by the CPU core?
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class InstructionBus(Elaboratable):
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def __init__(self):
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self.adr = Signal(30)
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self.dat_w = Signal(32)
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self.dat_r = Signal(32)
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self.sel = Signal(4)
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self.cyc = Signal(1)
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self.stb = Signal(1)
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self.ack = Signal(1)
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self.we = Signal(1)
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self.cti = Signal(3)
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self.bte = Signal(2)
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self.err = Signal(1)
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def ports(self):
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input_ports = [
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self.adr,
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self.dat_w,
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self.sel,
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self.cyc,
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self.stb,
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self.we,
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self.cti,
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self.bte
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]
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output_ports = [
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self.dat_r,
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self.ack,
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self.err
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]
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return input_ports + output_ports
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def elaborate(self, platform):
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m = Module()
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# TODO
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return m
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