468 lines
18 KiB
Python
468 lines
18 KiB
Python
from abc import abstractproperty
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from ..hdl import *
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from ..lib.cdc import ResetSynchronizer
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from ..build import *
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__all__ = ["XilinxSpartan3APlatform", "XilinxSpartan6Platform"]
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# The interface to Spartan 3 and 6 are substantially the same. Handle
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# differences internally using one class and expose user-aliases for
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# convenience.
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class XilinxSpartan3Or6Platform(TemplatedPlatform):
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"""
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Required tools:
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* ISE toolchain:
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* ``xst``
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* ``ngdbuild``
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* ``map``
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* ``par``
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* ``bitgen``
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The environment is populated by running the script specified in the environment variable
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``NMIGEN_ENV_ISE``, if present.
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Available overrides:
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* ``script_after_run``: inserts commands after ``run`` in XST script.
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* ``add_constraints``: inserts commands in UCF file.
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* ``xst_opts``: adds extra options for ``xst``.
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* ``ngdbuild_opts``: adds extra options for ``ngdbuild``.
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* ``map_opts``: adds extra options for ``map``.
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* ``par_opts``: adds extra options for ``par``.
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* ``bitgen_opts``: adds extra and overrides default options for ``bitgen``;
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default options: ``-g Compress``.
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Build products:
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* ``{{name}}.srp``: synthesis report.
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* ``{{name}}.ngc``: synthesized RTL.
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* ``{{name}}.bld``: NGDBuild log.
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* ``{{name}}.ngd``: design database.
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* ``{{name}}_map.map``: MAP log.
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* ``{{name}}_map.mrp``: mapping report.
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* ``{{name}}_map.ncd``: mapped netlist.
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* ``{{name}}.pcf``: physical constraints.
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* ``{{name}}_par.par``: PAR log.
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* ``{{name}}_par_pad.txt``: I/O usage report.
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* ``{{name}}_par.ncd``: place and routed netlist.
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* ``{{name}}.drc``: DRC report.
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* ``{{name}}.bgn``: BitGen log.
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* ``{{name}}.bit``: binary bitstream with metadata.
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* ``{{name}}.bin``: raw binary bitstream.
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"""
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toolchain = "ISE"
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device = abstractproperty()
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package = abstractproperty()
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speed = abstractproperty()
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required_tools = [
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"yosys",
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"xst",
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"ngdbuild",
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"map",
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"par",
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"bitgen",
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]
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@property
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def family(self):
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device = self.device.upper()
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if device.startswith("XC3S"):
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if device.endswith("A"):
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return "3A"
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elif device.endswith("E"):
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raise NotImplementedError("""Spartan 3E family is not supported
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as a nMigen platform.""")
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else:
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raise NotImplementedError("""Spartan 3 family is not supported
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as a nMigen platform.""")
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elif device.startswith("XC6S"):
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return "6"
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else:
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assert False
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file_templates = {
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**TemplatedPlatform.build_script_templates,
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"build_{{name}}.sh": r"""
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# {{autogenerated}}
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set -e{{verbose("x")}}
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if [ -z "$BASH" ] ; then exec /bin/bash "$0" "$@"; fi
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[ -n "${{platform._toolchain_env_var}}" ] && . "${{platform._toolchain_env_var}}"
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{{emit_commands("sh")}}
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""",
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"{{name}}.v": r"""
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/* {{autogenerated}} */
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{{emit_verilog()}}
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""",
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"{{name}}.debug.v": r"""
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/* {{autogenerated}} */
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{{emit_debug_verilog()}}
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""",
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"{{name}}.prj": r"""
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# {{autogenerated}}
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{% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
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vhdl work {{file}}
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{% endfor %}
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{% for file in platform.iter_extra_files(".v") -%}
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verilog work {{file}}
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{% endfor %}
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verilog work {{name}}.v
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""",
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"{{name}}.xst": r"""
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# {{autogenerated}}
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run
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-ifn {{name}}.prj
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-ofn {{name}}.ngc
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-top {{name}}
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{% if platform.family in ["3", "3E", "3A"] %}
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-use_new_parser yes
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{% endif %}
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-p {{platform.device}}{{platform.package}}-{{platform.speed}}
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{{get_override("script_after_run")|default("# (script_after_run placeholder)")}}
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""",
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"{{name}}.ucf": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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{% set port_name = port_name|replace("[", "<")|replace("]", ">") -%}
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NET "{{port_name}}" LOC={{pin_name}};
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{% for attr_name, attr_value in attrs.items() -%}
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NET "{{port_name}}" {{attr_name}}={{attr_value}};
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{% endfor %}
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{% endfor %}
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{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
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NET "{{net_signal|hierarchy("/")}}" TNM_NET="PRD{{net_signal|hierarchy("/")}}";
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TIMESPEC "TS{{net_signal|hierarchy("/")}}"=PERIOD "PRD{{net_signal|hierarchy("/")}}" {{1000000000/frequency}} ns HIGH 50%;
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{% endfor %}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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"""
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}
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command_templates = [
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r"""
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{{invoke_tool("xst")}}
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{{get_override("xst_opts")|options}}
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-ifn {{name}}.xst
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""",
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r"""
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{{invoke_tool("ngdbuild")}}
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{{quiet("-quiet")}}
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{{verbose("-verbose")}}
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{{get_override("ngdbuild_opts")|options}}
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-uc {{name}}.ucf
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{{name}}.ngc
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""",
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r"""
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{{invoke_tool("map")}}
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{{verbose("-detail")}}
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{{get_override("map_opts")|default([])|options}}
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-w
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-o {{name}}_map.ncd
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{{name}}.ngd
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{{name}}.pcf
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""",
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r"""
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{{invoke_tool("par")}}
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{{get_override("par_opts")|default([])|options}}
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-w
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{{name}}_map.ncd
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{{name}}_par.ncd
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{{name}}.pcf
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""",
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r"""
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{{invoke_tool("bitgen")}}
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{{get_override("bitgen_opts")|default(["-g Compress"])|options}}
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-w
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-g Binary:Yes
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{{name}}_par.ncd
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{{name}}.bit
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"""
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]
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def create_missing_domain(self, name):
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# Xilinx devices have a global write enable (GWE) signal that asserted during configuraiton
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# and deasserted once it ends. Because it is an asynchronous signal (GWE is driven by logic
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# syncronous to configuration clock, which is not used by most designs), even though it is
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# a low-skew global network, its deassertion may violate a setup/hold constraint with
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# relation to a user clock. The recommended solution is to use a BUFGCE driven by the EOS
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# signal (if available). For details, see:
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# * https://www.xilinx.com/support/answers/44174.html
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# * https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
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if self.family != "6":
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# Spartan 3 lacks a STARTUP primitive with EOS output; use a simple ResetSynchronizer
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# in that case, as is the default.
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return super().create_missing_domain(name)
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if name == "sync" and self.default_clk is not None:
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clk_i = self.request(self.default_clk).i
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if self.default_rst is not None:
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rst_i = self.request(self.default_rst).i
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m = Module()
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eos = Signal()
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m.submodules += Instance("STARTUP_SPARTAN6", o_EOS=eos)
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m.domains += ClockDomain("sync", reset_less=self.default_rst is None)
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m.submodules += Instance("BUFGCE", i_CE=eos, i_I=clk_i, o_O=ClockSignal("sync"))
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if self.default_rst is not None:
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m.submodules.reset_sync = ResetSynchronizer(rst_i, domain="sync")
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return m
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def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
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def get_dff(clk, d, q):
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# SDR I/O is performed by packing a flip-flop into the pad IOB.
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for bit in range(len(q)):
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m.submodules += Instance("FDCE",
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a_IOB="TRUE",
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i_C=clk,
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i_CE=Const(1),
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i_CLR=Const(0),
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i_D=d[bit],
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o_Q=q[bit]
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)
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def get_iddr(clk, d, q0, q1):
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for bit in range(len(q0)):
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m.submodules += Instance("IDDR2",
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p_DDR_ALIGNMENT="C0",
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p_SRTYPE="ASYNC",
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p_INIT_Q0=0, p_INIT_Q1=0,
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i_C0=clk, i_C1=~clk,
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i_CE=Const(1),
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i_S=Const(0), i_R=Const(0),
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i_D=d[bit],
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o_Q0=q0[bit], o_Q1=q1[bit]
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)
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def get_oddr(clk, d0, d1, q):
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for bit in range(len(q)):
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m.submodules += Instance("ODDR2",
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p_DDR_ALIGNMENT="C0",
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p_SRTYPE="ASYNC",
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p_INIT=0,
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i_C0=clk, i_C1=~clk,
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i_CE=Const(1),
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i_S=Const(0), i_R=Const(0),
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i_D0=d0[bit], i_D1=d1[bit],
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o_Q=q[bit]
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)
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def get_ineg(y, invert):
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if invert:
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a = Signal.like(y, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return a
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else:
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return y
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def get_oneg(a, invert):
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if invert:
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y = Signal.like(a, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return y
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else:
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return a
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ineg(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oneg(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
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i = o = t = None
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if "i" in pin.dir:
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i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
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if "o" in pin.dir:
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o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
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if pin.dir in ("oe", "io"):
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t = Signal(1, name="{}_xdr_t".format(pin.name))
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if pin.xdr == 0:
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if "i" in pin.dir:
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i = pin_i
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if "o" in pin.dir:
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o = pin_o
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if pin.dir in ("oe", "io"):
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t = ~pin.oe
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elif pin.xdr == 1:
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if "i" in pin.dir:
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get_dff(pin.i_clk, i, pin_i)
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if "o" in pin.dir:
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get_dff(pin.o_clk, pin_o, o)
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if pin.dir in ("oe", "io"):
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get_dff(pin.o_clk, ~pin.oe, t)
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elif pin.xdr == 2:
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if "i" in pin.dir:
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# Re-register first input before it enters fabric. This allows both inputs to
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# enter fabric on the same clock edge, and adds one cycle of latency.
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i0_ff = Signal.like(pin_i0, name_suffix="_ff")
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get_dff(pin.i_clk, i0_ff, pin_i0)
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get_iddr(pin.i_clk, i, i0_ff, pin_i1)
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if "o" in pin.dir:
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get_oddr(pin.o_clk, pin_o0, pin_o1, o)
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if pin.dir in ("oe", "io"):
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get_dff(pin.o_clk, ~pin.oe, t)
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else:
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assert False
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return (i, o, t)
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def get_input(self, pin, port, attrs, invert):
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self._check_feature("single-ended input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUF",
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i_I=port[bit],
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o_O=i[bit]
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)
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return m
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def get_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUF",
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_tristate(self, pin, port, attrs, invert):
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self._check_feature("single-ended tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFT",
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i_T=t,
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i_I=o[bit],
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o_O=port[bit]
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)
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return m
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def get_input_output(self, pin, port, attrs, invert):
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self._check_feature("single-ended input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
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for bit in range(len(port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUF",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_IO=port[bit]
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)
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return m
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def get_diff_input(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IBUFDS",
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i_I=p_port[bit], i_IB=n_port[bit],
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o_O=i[bit]
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)
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return m
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def get_diff_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFDS",
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i_I=o[bit],
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o_O=p_port[bit], o_OB=n_port[bit]
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)
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return m
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def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential tristate", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("OBUFTDS",
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i_T=t,
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i_I=o[bit],
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o_O=p_port[bit], o_OB=n_port[bit]
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)
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return m
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def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
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self._check_feature("differential input/output", pin, attrs,
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valid_xdrs=(0, 1, 2), valid_attrs=True)
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m = Module()
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i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
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for bit in range(len(p_port)):
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m.submodules["{}_{}".format(pin.name, bit)] = Instance("IOBUFDS",
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i_T=t,
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i_I=o[bit],
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o_O=i[bit],
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io_IO=p_port[bit], io_IOB=n_port[bit]
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)
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return m
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# The synchronizer implementations below apply the ASYNC_REG attribute. This attribute
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# prevents inference of shift registers from synchronizer FFs, and constraints the FFs
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# to be placed as close as possible, ideally in one CLB. This attribute only affects
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# the synchronizer FFs themselves.
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def get_ff_sync(self, ff_sync):
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if ff_sync._max_input_delay is not None:
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raise NotImplementedError("Platform '{}' does not support constraining input delay "
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"for FFSynchronizer"
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.format(type(self).__name__))
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m = Module()
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flops = [Signal(ff_sync.i.shape(), name="stage{}".format(index),
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reset=ff_sync._reset, reset_less=ff_sync._reset_less,
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attrs={"ASYNC_REG": "TRUE"})
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for index in range(ff_sync._stages)]
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for i, o in zip((ff_sync.i, *flops), flops):
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m.d[ff_sync._o_domain] += o.eq(i)
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m.d.comb += ff_sync.o.eq(flops[-1])
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return m
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def get_async_ff_sync(self, async_ff_sync):
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if self._max_input_delay is not None:
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raise NotImplementedError("Platform '{}' does not support constraining input delay "
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"for AsyncFFSynchronizer"
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.format(type(self).__name__))
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m = Module()
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m.domains += ClockDomain("async_ff", async_reset=True, local=True)
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flops = [Signal(1, name="stage{}".format(index), reset=1,
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attrs={"ASYNC_REG": "TRUE"})
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for index in range(async_ff_sync._stages)]
|
|
for i, o in zip((0, *flops), flops):
|
|
m.d.async_ff += o.eq(i)
|
|
|
|
if async_ff_sync._edge == "pos":
|
|
m.d.comb += ResetSignal("async_ff").eq(asnyc_ff_sync.i)
|
|
else:
|
|
m.d.comb += ResetSignal("async_ff").eq(~asnyc_ff_sync.i)
|
|
|
|
m.d.comb += [
|
|
ClockSignal("async_ff").eq(ClockSignal(asnyc_ff_sync._domain)),
|
|
async_ff_sync.o.eq(flops[-1])
|
|
]
|
|
|
|
return m
|
|
|
|
XilinxSpartan3APlatform = XilinxSpartan3Or6Platform
|
|
XilinxSpartan6Platform = XilinxSpartan3Or6Platform
|