586 lines
24 KiB
Python
586 lines
24 KiB
Python
from abc import abstractproperty
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from ..hdl import *
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from ..lib.cdc import ResetSynchronizer
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from ..build import *
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__all__ = ["LatticeICE40Platform"]
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class LatticeICE40Platform(TemplatedPlatform):
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"""
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IceStorm toolchain
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------------------
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Required tools:
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* ``yosys``
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* ``nextpnr-ice40``
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* ``icepack``
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The environment is populated by running the script specified in the environment variable
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``NMIGEN_ENV_IceStorm``, if present.
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Available overrides:
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* ``verbose``: enables logging of informational messages to standard error.
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* ``read_verilog_opts``: adds options for ``read_verilog`` Yosys command.
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* ``synth_opts``: adds options for ``synth_ice40`` Yosys command.
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* ``script_after_read``: inserts commands after ``read_ilang`` in Yosys script.
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* ``script_after_synth``: inserts commands after ``synth_ice40`` in Yosys script.
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* ``yosys_opts``: adds extra options for ``yosys``.
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* ``nextpnr_opts``: adds extra options for ``nextpnr-ice40``.
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* ``add_pre_pack``: inserts commands at the end in pre-pack Python script.
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* ``add_constraints``: inserts commands at the end in the PCF file.
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Build products:
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* ``{{name}}.rpt``: Yosys log.
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* ``{{name}}.json``: synthesized RTL.
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* ``{{name}}.tim``: nextpnr log.
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* ``{{name}}.asc``: ASCII bitstream.
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* ``{{name}}.bin``: binary bitstream.
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iCECube2 toolchain
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------------------
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This toolchain comes in two variants: ``LSE-iCECube2`` and ``Synplify-iCECube2``.
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Required tools:
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* iCECube2 toolchain
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* ``tclsh``
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The environment is populated by setting the necessary environment variables based on
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``NMIGEN_ENV_iCECube2``, which must point to the root of the iCECube2 installation, and
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is required.
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Available overrides:
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* ``verbose``: enables logging of informational messages to standard error.
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* ``lse_opts``: adds options for LSE.
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* ``script_after_add``: inserts commands after ``add_file`` in Synplify Tcl script.
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* ``script_after_options``: inserts commands after ``set_option`` in Synplify Tcl script.
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* ``add_constraints``: inserts commands in SDC file.
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* ``script_after_flow``: inserts commands after ``run_sbt_backend_auto`` in SBT
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Tcl script.
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Build products:
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* ``{{name}}_lse.log`` (LSE) or ``{{name}}_design/{{name}}.htm`` (Synplify): synthesis log.
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* ``sbt/outputs/router/{{name}}_timing.rpt``: timing report.
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* ``{{name}}.edf``: EDIF netlist.
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* ``{{name}}.bin``: binary bitstream.
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"""
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toolchain = None # selected when creating platform
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device = abstractproperty()
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package = abstractproperty()
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# IceStorm templates
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_nextpnr_device_options = {
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"iCE40LP384": "--lp384",
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"iCE40LP1K": "--lp1k",
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"iCE40LP4K": "--lp8k",
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"iCE40LP8K": "--lp8k",
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"iCE40HX1K": "--hx1k",
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"iCE40HX4K": "--hx8k",
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"iCE40HX8K": "--hx8k",
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"iCE40UP5K": "--up5k",
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"iCE40UP3K": "--up5k",
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"iCE5LP4K": "--u4k",
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"iCE5LP2K": "--u4k",
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"iCE5LP1K": "--u4k",
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}
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_nextpnr_package_options = {
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"iCE40LP4K": ":4k",
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"iCE40HX4K": ":4k",
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"iCE40UP3K": "",
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"iCE5LP2K": "",
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"iCE5LP1K": "",
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}
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_icestorm_required_tools = [
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"yosys",
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"nextpnr-ice40",
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"icepack",
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]
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_icestorm_file_templates = {
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**TemplatedPlatform.build_script_templates,
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"{{name}}.il": r"""
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# {{autogenerated}}
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{{emit_rtlil()}}
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""",
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"{{name}}.debug.v": r"""
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/* {{autogenerated}} */
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{{emit_debug_verilog()}}
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""",
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"{{name}}.ys": r"""
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# {{autogenerated}}
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{% for file in platform.iter_extra_files(".v") -%}
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read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
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{% endfor %}
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{% for file in platform.iter_extra_files(".sv") -%}
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read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
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{% endfor %}
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{% for file in platform.iter_extra_files(".il") -%}
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read_ilang {{file}}
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{% endfor %}
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read_ilang {{name}}.il
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{{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
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synth_ice40 {{get_override("synth_opts")|options}} -top {{name}}
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{{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
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write_json {{name}}.json
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""",
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"{{name}}.pcf": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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set_io {{port_name}} {{pin_name}}
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{% endfor %}
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{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
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set_frequency {{net_signal|hierarchy(".")}} {{frequency/1000000}}
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{% endfor%}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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""",
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}
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_icestorm_command_templates = [
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r"""
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{{invoke_tool("yosys")}}
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{{quiet("-q")}}
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{{get_override("yosys_opts")|options}}
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-l {{name}}.rpt
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{{name}}.ys
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""",
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r"""
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{{invoke_tool("nextpnr-ice40")}}
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{{quiet("--quiet")}}
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{{get_override("nextpnr_opts")|options}}
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--log {{name}}.tim
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{{platform._nextpnr_device_options[platform.device]}}
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--package
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{{platform.package|lower}}{{platform._nextpnr_package_options[platform.device]}}
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--json {{name}}.json
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--pcf {{name}}.pcf
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--asc {{name}}.asc
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""",
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r"""
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{{invoke_tool("icepack")}}
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{{verbose("-v")}}
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{{name}}.asc
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{{name}}.bin
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"""
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]
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# iCECube2 templates
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_icecube2_required_tools = [
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"yosys",
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"synthesis",
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"synpwrap",
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"tclsh",
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]
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_icecube2_file_templates = {
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**TemplatedPlatform.build_script_templates,
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"build_{{name}}.sh": r"""
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# {{autogenerated}}
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set -e{{verbose("x")}}
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if [ -n "${{platform._toolchain_env_var}}" ]; then
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# LSE environment
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export LD_LIBRARY_PATH=${{platform._toolchain_env_var}}/LSE/bin/lin64:$LD_LIBRARY_PATH
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export PATH=${{platform._toolchain_env_var}}/LSE/bin/lin64:$PATH
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export FOUNDRY=${{platform._toolchain_env_var}}/LSE
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# Synplify environment
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export LD_LIBRARY_PATH=${{platform._toolchain_env_var}}/sbt_backend/bin/linux/opt/synpwrap:$LD_LIBRARY_PATH
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export PATH=${{platform._toolchain_env_var}}/sbt_backend/bin/linux/opt/synpwrap:$PATH
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export SYNPLIFY_PATH=${{platform._toolchain_env_var}}/synpbase
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# Common environment
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export SBT_DIR=${{platform._toolchain_env_var}}/sbt_backend
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else
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echo "Variable ${{platform._toolchain_env_var}} must be set" >&2; exit 1
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fi
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{{emit_commands("sh")}}
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""",
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"{{name}}.v": r"""
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/* {{autogenerated}} */
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{{emit_verilog()}}
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""",
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"{{name}}.debug.v": r"""
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/* {{autogenerated}} */
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{{emit_debug_verilog()}}
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""",
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"{{name}}_lse.prj": r"""
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# {{autogenerated}}
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-a SBT{{platform.family}}
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-d {{platform.device}}
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-t {{platform.package}}
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{{get_override("lse_opts")|options|default("# (lse_opts placeholder)")}}
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{% for file in platform.iter_extra_files(".v") -%}
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-ver {{file}}
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{% endfor %}
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-ver {{name}}.v
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-sdc {{name}}.sdc
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-top {{name}}
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-output_edif {{name}}.edf
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-logfile {{name}}_lse.log
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""",
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"{{name}}_syn.prj": r"""
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# {{autogenerated}}
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{% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
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add_file -verilog {{file}}
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{% endfor %}
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add_file -verilog {{name}}.v
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add_file -constraint {{name}}.sdc
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{{get_override("script_after_add")|default("# (script_after_add placeholder)")}}
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impl -add {{name}}_design -type fpga
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set_option -technology SBT{{platform.family}}
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set_option -part {{platform.device}}
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set_option -package {{platform.package}}
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{{get_override("script_after_options")|default("# (script_after_options placeholder)")}}
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project -result_format edif
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project -result_file {{name}}.edf
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impl -active {{name}}_design
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project -run compile
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project -run map
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project -run fpga_mapper
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file copy -force -- {{name}}_design/{{name}}.edf {{name}}.edf
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""",
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"{{name}}.sdc": r"""
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# {{autogenerated}}
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{% for net_signal, port_signal, frequency in platform.iter_clock_constraints() -%}
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{% if port_signal is not none -%}
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create_clock -name {{port_signal.name}} -period {{1000000000/frequency}} [get_ports {{port_signal.name}}]
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{% else -%}
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create_clock -name {{net_signal.name}} -period {{1000000000/frequency}} [get_nets {{net_signal|hierarchy("/")}}]
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{% endif %}
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{% endfor %}
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{{get_override("add_constraints")|default("# (add_constraints placeholder)")}}
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""",
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"{{name}}.tcl": r"""
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# {{autogenerated}}
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set device {{platform.device}}-{{platform.package}}
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set top_module {{name}}
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set proj_dir .
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set output_dir .
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set edif_file {{name}}
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set tool_options ":edifparser -y {{name}}.pcf"
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set sbt_root $::env(SBT_DIR)
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append sbt_tcl $sbt_root "/tcl/sbt_backend_synpl.tcl"
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source $sbt_tcl
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run_sbt_backend_auto $device $top_module $proj_dir $output_dir $tool_options $edif_file
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{{get_override("script_after_file")|default("# (script_after_file placeholder)")}}
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file copy -force -- sbt/outputs/bitmap/{{name}}_bitmap.bin {{name}}.bin
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exit
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""",
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"{{name}}.pcf": r"""
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# {{autogenerated}}
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{% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
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set_io {{port_name}} {{pin_name}}
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{% endfor %}
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""",
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}
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_lse_icecube2_command_templates = [
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r"""synthesis -f {{name}}_lse.prj""",
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r"""tclsh {{name}}.tcl""",
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]
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_synplify_icecube2_command_templates = [
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r"""synpwrap -prj {{name}}_syn.prj -log {{name}}_syn.log""",
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r"""tclsh {{name}}.tcl""",
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]
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# Common logic
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def __init__(self, *, toolchain="IceStorm"):
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super().__init__()
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assert toolchain in ("IceStorm", "LSE-iCECube2", "Synplify-iCECube2")
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self.toolchain = toolchain
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@property
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def family(self):
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if self.device.startswith("iCE40"):
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return "iCE40"
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if self.device.startswith("iCE5"):
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return "iCE5"
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assert False
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@property
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def _toolchain_env_var(self):
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if self.toolchain == "IceStorm":
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return f"NMIGEN_ENV_{self.toolchain}"
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if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
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return f"NMIGEN_ENV_iCECube2"
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assert False
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@property
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def required_tools(self):
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if self.toolchain == "IceStorm":
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return self._icestorm_required_tools
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if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
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return self._icecube2_required_tools
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assert False
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@property
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def file_templates(self):
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if self.toolchain == "IceStorm":
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return self._icestorm_file_templates
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if self.toolchain in ("LSE-iCECube2", "Synplify-iCECube2"):
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return self._icecube2_file_templates
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assert False
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@property
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def command_templates(self):
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if self.toolchain == "IceStorm":
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return self._icestorm_command_templates
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if self.toolchain == "LSE-iCECube2":
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return self._lse_icecube2_command_templates
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if self.toolchain == "Synplify-iCECube2":
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return self._synplify_icecube2_command_templates
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assert False
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def create_missing_domain(self, name):
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# For unknown reasons (no errata was ever published, and no documentation mentions this
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# issue), iCE40 BRAMs read as zeroes for ~3 us after configuration and release of internal
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# global reset. Note that this is a *time-based* delay, generated purely by the internal
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# oscillator, which may not be observed nor influenced directly. For details, see links:
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# * https://github.com/cliffordwolf/icestorm/issues/76#issuecomment-289270411
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# * https://github.com/cliffordwolf/icotools/issues/2#issuecomment-299734673
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#
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# To handle this, it is necessary to have a global reset in any iCE40 design that may
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# potentially instantiate BRAMs, and assert this reset for >3 us after configuration.
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# (We add a margin of 5x to allow for PVT variation.) If the board includes a dedicated
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# reset line, this line is ORed with the power on reset.
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#
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# The power-on reset timer counts up because the vendor tools do not support initialization
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# of flip-flops.
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if name == "sync" and self.default_clk is not None:
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clk_i = self.request(self.default_clk).i
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if self.default_rst is not None:
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rst_i = self.request(self.default_rst).i
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else:
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rst_i = Const(0)
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m = Module()
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# Power-on-reset domain
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m.domains += ClockDomain("por", reset_less=True, local=True)
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delay = int(15e-6 * self.default_clk_frequency)
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timer = Signal(range(delay))
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ready = Signal()
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m.d.comb += ClockSignal("por").eq(clk_i)
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with m.If(timer == delay):
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m.d.por += ready.eq(1)
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with m.Else():
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m.d.por += timer.eq(timer + 1)
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# Primary domain
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m.domains += ClockDomain("sync")
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m.d.comb += ClockSignal("sync").eq(clk_i)
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if self.default_rst is not None:
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m.submodules.reset_sync = ResetSynchronizer(~ready | rst_i, domain="sync")
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else:
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m.d.comb += ResetSignal("sync").eq(~ready)
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return m
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def should_skip_port_component(self, port, attrs, component):
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# On iCE40, a differential input is placed by only instantiating an SB_IO primitive for
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# the pin with z=0, which is the non-inverting pin. The pinout unfortunately differs
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# between LP/HX and UP series:
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# * for LP/HX, z=0 is DPxxB (B is non-inverting, A is inverting)
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# * for UP, z=0 is IOB_xxA (A is non-inverting, B is inverting)
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if attrs.get("IO_STANDARD", "SB_LVCMOS") == "SB_LVDS_INPUT" and component == "n":
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return True
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return False
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def _get_io_buffer(self, m, pin, port, attrs, *, i_invert=False, o_invert=False,
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invert_lut=False):
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def get_dff(clk, d, q):
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m.submodules += Instance("$dff",
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p_CLK_POLARITY=1,
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p_WIDTH=len(d),
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i_CLK=clk,
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i_D=d,
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o_Q=q)
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def get_ineg(y, invert):
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if invert_lut:
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a = Signal.like(y, name_suffix="_x{}".format(1 if invert else 0))
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for bit in range(len(y)):
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
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i_I0=a[bit],
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i_I1=Const(0),
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i_I2=Const(0),
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i_I3=Const(0),
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o_O=y[bit])
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return a
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elif invert:
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a = Signal.like(y, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return a
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else:
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return y
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def get_oneg(a, invert):
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if invert_lut:
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y = Signal.like(a, name_suffix="_x{}".format(1 if invert else 0))
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for bit in range(len(a)):
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m.submodules += Instance("SB_LUT4",
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p_LUT_INIT=Const(0b01 if invert else 0b10, 16),
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i_I0=a[bit],
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i_I1=Const(0),
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i_I2=Const(0),
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i_I3=Const(0),
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o_O=y[bit])
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return y
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elif invert:
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y = Signal.like(a, name_suffix="_n")
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m.d.comb += y.eq(~a)
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return y
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else:
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return a
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if "GLOBAL" in attrs:
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is_global_input = bool(attrs["GLOBAL"])
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del attrs["GLOBAL"]
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else:
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is_global_input = False
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assert not (is_global_input and i_invert)
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if "i" in pin.dir:
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if pin.xdr < 2:
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pin_i = get_ineg(pin.i, i_invert)
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elif pin.xdr == 2:
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pin_i0 = get_ineg(pin.i0, i_invert)
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pin_i1 = get_ineg(pin.i1, i_invert)
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if "o" in pin.dir:
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if pin.xdr < 2:
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pin_o = get_oneg(pin.o, o_invert)
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elif pin.xdr == 2:
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pin_o0 = get_oneg(pin.o0, o_invert)
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pin_o1 = get_oneg(pin.o1, o_invert)
|
|
|
|
if "i" in pin.dir and pin.xdr == 2:
|
|
i0_ff = Signal.like(pin_i0, name_suffix="_ff")
|
|
i1_ff = Signal.like(pin_i1, name_suffix="_ff")
|
|
get_dff(pin.i_clk, i0_ff, pin_i0)
|
|
get_dff(pin.i_clk, i1_ff, pin_i1)
|
|
if "o" in pin.dir and pin.xdr == 2:
|
|
o1_ff = Signal.like(pin_o1, name_suffix="_ff")
|
|
get_dff(pin.o_clk, pin_o1, o1_ff)
|
|
|
|
for bit in range(len(port)):
|
|
io_args = [
|
|
("io", "PACKAGE_PIN", port[bit]),
|
|
*(("p", key, value) for key, value in attrs.items()),
|
|
]
|
|
|
|
if "i" not in pin.dir:
|
|
# If no input pin is requested, it is important to use a non-registered input pin
|
|
# type, because an output-only pin would not have an input clock, and if its input
|
|
# is configured as registered, this would prevent a co-located input-capable pin
|
|
# from using an input clock.
|
|
i_type = 0b01 # PIN_INPUT
|
|
elif pin.xdr == 0:
|
|
i_type = 0b01 # PIN_INPUT
|
|
elif pin.xdr > 0:
|
|
i_type = 0b00 # PIN_INPUT_REGISTERED aka PIN_INPUT_DDR
|
|
if "o" not in pin.dir:
|
|
o_type = 0b0000 # PIN_NO_OUTPUT
|
|
elif pin.xdr == 0 and pin.dir == "o":
|
|
o_type = 0b0110 # PIN_OUTPUT
|
|
elif pin.xdr == 0:
|
|
o_type = 0b1010 # PIN_OUTPUT_TRISTATE
|
|
elif pin.xdr == 1 and pin.dir == "o":
|
|
o_type = 0b0101 # PIN_OUTPUT_REGISTERED
|
|
elif pin.xdr == 1:
|
|
o_type = 0b1101 # PIN_OUTPUT_REGISTERED_ENABLE_REGISTERED
|
|
elif pin.xdr == 2 and pin.dir == "o":
|
|
o_type = 0b0100 # PIN_OUTPUT_DDR
|
|
elif pin.xdr == 2:
|
|
o_type = 0b1100 # PIN_OUTPUT_DDR_ENABLE_REGISTERED
|
|
io_args.append(("p", "PIN_TYPE", C((o_type << 2) | i_type, 6)))
|
|
|
|
if hasattr(pin, "i_clk"):
|
|
io_args.append(("i", "INPUT_CLK", pin.i_clk))
|
|
if hasattr(pin, "o_clk"):
|
|
io_args.append(("i", "OUTPUT_CLK", pin.o_clk))
|
|
|
|
if "i" in pin.dir:
|
|
if pin.xdr == 0 and is_global_input:
|
|
io_args.append(("o", "GLOBAL_BUFFER_OUTPUT", pin.i[bit]))
|
|
elif pin.xdr < 2:
|
|
io_args.append(("o", "D_IN_0", pin_i[bit]))
|
|
elif pin.xdr == 2:
|
|
# Re-register both inputs before they enter fabric. This increases hold time
|
|
# to an entire cycle, and adds one cycle of latency.
|
|
io_args.append(("o", "D_IN_0", i0_ff[bit]))
|
|
io_args.append(("o", "D_IN_1", i1_ff[bit]))
|
|
if "o" in pin.dir:
|
|
if pin.xdr < 2:
|
|
io_args.append(("i", "D_OUT_0", pin_o[bit]))
|
|
elif pin.xdr == 2:
|
|
# Re-register negedge output after it leaves fabric. This increases setup time
|
|
# to an entire cycle, and doesn't add latency.
|
|
io_args.append(("i", "D_OUT_0", pin_o0[bit]))
|
|
io_args.append(("i", "D_OUT_1", o1_ff[bit]))
|
|
|
|
if pin.dir in ("oe", "io"):
|
|
io_args.append(("i", "OUTPUT_ENABLE", pin.oe))
|
|
|
|
if is_global_input:
|
|
m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_GB_IO", *io_args)
|
|
else:
|
|
m.submodules["{}_{}".format(pin.name, bit)] = Instance("SB_IO", *io_args)
|
|
|
|
def get_input(self, pin, port, attrs, invert):
|
|
self._check_feature("single-ended input", pin, attrs,
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
|
m = Module()
|
|
self._get_io_buffer(m, pin, port, attrs, i_invert=invert)
|
|
return m
|
|
|
|
def get_output(self, pin, port, attrs, invert):
|
|
self._check_feature("single-ended output", pin, attrs,
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
|
m = Module()
|
|
self._get_io_buffer(m, pin, port, attrs, o_invert=invert)
|
|
return m
|
|
|
|
def get_tristate(self, pin, port, attrs, invert):
|
|
self._check_feature("single-ended tristate", pin, attrs,
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
|
m = Module()
|
|
self._get_io_buffer(m, pin, port, attrs, o_invert=invert)
|
|
return m
|
|
|
|
def get_input_output(self, pin, port, attrs, invert):
|
|
self._check_feature("single-ended input/output", pin, attrs,
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
|
m = Module()
|
|
self._get_io_buffer(m, pin, port, attrs, i_invert=invert, o_invert=invert)
|
|
return m
|
|
|
|
def get_diff_input(self, pin, p_port, n_port, attrs, invert):
|
|
self._check_feature("differential input", pin, attrs,
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
|
m = Module()
|
|
# See comment in should_skip_port_component above.
|
|
self._get_io_buffer(m, pin, p_port, attrs, i_invert=invert)
|
|
return m
|
|
|
|
def get_diff_output(self, pin, p_port, n_port, attrs, invert):
|
|
self._check_feature("differential output", pin, attrs,
|
|
valid_xdrs=(0, 1, 2), valid_attrs=True)
|
|
m = Module()
|
|
# Note that the non-inverting output pin is not driven the same way as a regular
|
|
# output pin. The inverter introduces a delay, so for a non-inverting output pin,
|
|
# an identical delay is introduced by instantiating a LUT. This makes the waveform
|
|
# perfectly symmetric in the xdr=0 case.
|
|
self._get_io_buffer(m, pin, p_port, attrs, o_invert= invert, invert_lut=True)
|
|
self._get_io_buffer(m, pin, n_port, attrs, o_invert=not invert, invert_lut=True)
|
|
return m
|
|
|
|
# Tristate and bidirectional buffers are not supported on iCE40 because it requires external
|
|
# termination, which is incompatible for input and output differential I/Os.
|
|
|
|
# CDC primitives are not currently specialized for iCE40. It is not known if iCECube2 supports
|
|
# the necessary attributes; nextpnr-ice40 does not.
|