251 lines
11 KiB
Python
251 lines
11 KiB
Python
from collections import OrderedDict
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from ..hdl.ast import *
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from ..hdl.rec import *
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from ..lib.io import *
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from .dsl import *
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__all__ = ["ResourceError", "ResourceManager"]
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class ResourceError(Exception):
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pass
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class ResourceManager:
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def __init__(self, resources, connectors):
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self.resources = OrderedDict()
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self._requested = OrderedDict()
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self._phys_reqd = OrderedDict()
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self.connectors = OrderedDict()
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self._conn_pins = OrderedDict()
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# Constraint lists
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self._ports = []
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self._clocks = SignalDict()
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self.add_resources(resources)
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self.add_connectors(connectors)
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def add_resources(self, resources):
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for res in resources:
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if not isinstance(res, Resource):
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raise TypeError("Object {!r} is not a Resource".format(res))
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if (res.name, res.number) in self.resources:
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raise NameError("Trying to add {!r}, but {!r} has the same name and number"
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.format(res, self.resources[res.name, res.number]))
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self.resources[res.name, res.number] = res
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def add_connectors(self, connectors):
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for conn in connectors:
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if not isinstance(conn, Connector):
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raise TypeError("Object {!r} is not a Connector".format(conn))
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if (conn.name, conn.number) in self.connectors:
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raise NameError("Trying to add {!r}, but {!r} has the same name and number"
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.format(conn, self.connectors[conn.name, conn.number]))
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self.connectors[conn.name, conn.number] = conn
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for conn_pin, plat_pin in conn:
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assert conn_pin not in self._conn_pins
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self._conn_pins[conn_pin] = plat_pin
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def lookup(self, name, number=0):
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if (name, number) not in self.resources:
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raise ResourceError("Resource {}#{} does not exist"
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.format(name, number))
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return self.resources[name, number]
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def request(self, name, number=0, *, dir=None, xdr=None):
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resource = self.lookup(name, number)
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if (resource.name, resource.number) in self._requested:
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raise ResourceError("Resource {}#{} has already been requested"
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.format(name, number))
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def merge_options(subsignal, dir, xdr):
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if isinstance(subsignal.ios[0], Subsignal):
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if dir is None:
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dir = dict()
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if xdr is None:
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xdr = dict()
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if not isinstance(dir, dict):
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raise TypeError("Directions must be a dict, not {!r}, because {!r} "
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"has subsignals"
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.format(dir, subsignal))
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if not isinstance(xdr, dict):
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raise TypeError("Data rate must be a dict, not {!r}, because {!r} "
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"has subsignals"
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.format(xdr, subsignal))
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for sub in subsignal.ios:
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sub_dir = dir.get(sub.name, None)
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sub_xdr = xdr.get(sub.name, None)
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dir[sub.name], xdr[sub.name] = merge_options(sub, sub_dir, sub_xdr)
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else:
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if dir is None:
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dir = subsignal.ios[0].dir
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if xdr is None:
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xdr = 0
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if dir not in ("i", "o", "oe", "io", "-"):
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raise TypeError("Direction must be one of \"i\", \"o\", \"oe\", \"io\", "
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"or \"-\", not {!r}"
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.format(dir))
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if dir != subsignal.ios[0].dir and \
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not (subsignal.ios[0].dir == "io" or dir == "-"):
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raise ValueError("Direction of {!r} cannot be changed from \"{}\" to \"{}\"; "
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"direction can be changed from \"io\" to \"i\", \"o\", or "
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"\"oe\", or from anything to \"-\""
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.format(subsignal.ios[0], subsignal.ios[0].dir, dir))
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if not isinstance(xdr, int) or xdr < 0:
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raise ValueError("Data rate of {!r} must be a non-negative integer, not {!r}"
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.format(subsignal.ios[0], xdr))
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return dir, xdr
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def resolve(resource, dir, xdr, name, attrs):
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for attr_key, attr_value in attrs.items():
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if hasattr(attr_value, "__call__"):
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attr_value = attr_value(self)
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assert attr_value is None or isinstance(attr_value, str)
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if attr_value is None:
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del attrs[attr_key]
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else:
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attrs[attr_key] = attr_value
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if isinstance(resource.ios[0], Subsignal):
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fields = OrderedDict()
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for sub in resource.ios:
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fields[sub.name] = resolve(sub, dir[sub.name], xdr[sub.name],
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name="{}__{}".format(name, sub.name),
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attrs={**attrs, **sub.attrs})
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return Record([
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(f_name, f.layout) for (f_name, f) in fields.items()
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], fields=fields, name=name)
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elif isinstance(resource.ios[0], (Pins, DiffPairs)):
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phys = resource.ios[0]
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if isinstance(phys, Pins):
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phys_names = phys.names
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port = Record([("io", len(phys))], name=name)
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if isinstance(phys, DiffPairs):
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phys_names = phys.p.names + phys.n.names
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port = Record([("p", len(phys)),
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("n", len(phys))], name=name)
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if dir == "-":
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pin = None
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else:
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pin = Pin(len(phys), dir, xdr=xdr, name=name)
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for phys_name in phys_names:
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if phys_name in self._phys_reqd:
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raise ResourceError("Resource component {} uses physical pin {}, but it "
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"is already used by resource component {} that was "
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"requested earlier"
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.format(name, phys_name, self._phys_reqd[phys_name]))
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self._phys_reqd[phys_name] = name
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self._ports.append((resource, pin, port, attrs))
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if pin is not None and resource.clock is not None:
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self.add_clock_constraint(pin.i, resource.clock.frequency)
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return pin if pin is not None else port
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else:
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assert False # :nocov:
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value = resolve(resource,
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*merge_options(resource, dir, xdr),
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name="{}_{}".format(resource.name, resource.number),
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attrs=resource.attrs)
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self._requested[resource.name, resource.number] = value
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return value
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def iter_single_ended_pins(self):
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for res, pin, port, attrs in self._ports:
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if pin is None:
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continue
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if isinstance(res.ios[0], Pins):
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yield pin, port.io, attrs, res.ios[0].invert
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def iter_differential_pins(self):
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for res, pin, port, attrs in self._ports:
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if pin is None:
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continue
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if isinstance(res.ios[0], DiffPairs):
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yield pin, port.p, port.n, attrs, res.ios[0].invert
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def should_skip_port_component(self, port, attrs, component):
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return False
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def iter_ports(self):
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for res, pin, port, attrs in self._ports:
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if isinstance(res.ios[0], Pins):
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if not self.should_skip_port_component(port, attrs, "io"):
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yield port.io
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elif isinstance(res.ios[0], DiffPairs):
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if not self.should_skip_port_component(port, attrs, "p"):
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yield port.p
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if not self.should_skip_port_component(port, attrs, "n"):
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yield port.n
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else:
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assert False
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def iter_port_constraints(self):
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for res, pin, port, attrs in self._ports:
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if isinstance(res.ios[0], Pins):
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if not self.should_skip_port_component(port, attrs, "io"):
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yield port.io.name, res.ios[0].map_names(self._conn_pins, res), attrs
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elif isinstance(res.ios[0], DiffPairs):
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if not self.should_skip_port_component(port, attrs, "p"):
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yield port.p.name, res.ios[0].p.map_names(self._conn_pins, res), attrs
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if not self.should_skip_port_component(port, attrs, "n"):
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yield port.n.name, res.ios[0].n.map_names(self._conn_pins, res), attrs
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else:
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assert False
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def iter_port_constraints_bits(self):
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for port_name, pin_names, attrs in self.iter_port_constraints():
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if len(pin_names) == 1:
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yield port_name, pin_names[0], attrs
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else:
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for bit, pin_name in enumerate(pin_names):
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yield "{}[{}]".format(port_name, bit), pin_name, attrs
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def add_clock_constraint(self, clock, frequency):
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if not isinstance(clock, Signal):
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raise TypeError("Object {!r} is not a Signal".format(clock))
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if not isinstance(frequency, (int, float)):
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raise TypeError("Frequency must be a number, not {!r}".format(frequency))
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if clock in self._clocks:
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raise ValueError("Cannot add clock constraint on {!r}, which is already constrained "
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"to {} Hz"
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.format(clock, self._clocks[clock]))
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else:
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self._clocks[clock] = float(frequency)
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def iter_clock_constraints(self):
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# Back-propagate constraints through the input buffer. For clock constraints on pins
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# (the majority of cases), toolchains work better if the constraint is defined on the pin
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# and not on the buffered internal net; and if the toolchain is advanced enough that
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# it considers clock phase and delay of the input buffer, it is *necessary* to define
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# the constraint on the pin to match the designer's expectation of phase being referenced
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# to the pin.
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#
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# Constraints on nets with no corresponding input pin (e.g. PLL or SERDES outputs) are not
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# affected.
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pin_i_to_port = SignalDict()
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for res, pin, port, attrs in self._ports:
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if hasattr(pin, "i"):
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if isinstance(res.ios[0], Pins):
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pin_i_to_port[pin.i] = port.io
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elif isinstance(res.ios[0], DiffPairs):
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pin_i_to_port[pin.i] = port.p
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else:
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assert False
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for net_signal, frequency in self._clocks.items():
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port_signal = pin_i_to_port.get(net_signal)
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yield net_signal, port_signal, frequency
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