1129 lines
40 KiB
Python
1129 lines
40 KiB
Python
import os
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import tempfile
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import warnings
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import inspect
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from contextlib import contextmanager
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import itertools
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from vcd import VCDWriter
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from vcd.gtkw import GTKWSave
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from .._utils import deprecated
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from ..hdl.ast import *
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from ..hdl.cd import *
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from ..hdl.ir import *
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from ..hdl.xfrm import ValueVisitor, StatementVisitor, LHSGroupFilter
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class Command:
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pass
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class Settle(Command):
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def __repr__(self):
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return "(settle)"
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class Delay(Command):
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def __init__(self, interval=None):
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self.interval = None if interval is None else float(interval)
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def __repr__(self):
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if self.interval is None:
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return "(delay ε)"
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else:
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return "(delay {:.3}us)".format(self.interval * 1e6)
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class Tick(Command):
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def __init__(self, domain="sync"):
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if not isinstance(domain, (str, ClockDomain)):
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raise TypeError("Domain must be a string or a ClockDomain instance, not {!r}"
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.format(domain))
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assert domain != "comb"
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self.domain = domain
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def __repr__(self):
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return "(tick {})".format(self.domain)
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class Passive(Command):
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def __repr__(self):
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return "(passive)"
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class Active(Command):
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def __repr__(self):
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return "(active)"
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class _WaveformWriter:
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def update(self, timestamp, signal, value):
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raise NotImplementedError # :nocov:
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def close(self, timestamp):
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raise NotImplementedError # :nocov:
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class _VCDWaveformWriter(_WaveformWriter):
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@staticmethod
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def timestamp_to_vcd(timestamp):
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return timestamp * (10 ** 10) # 1/(100 ps)
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@staticmethod
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def decode_to_vcd(signal, value):
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return signal.decoder(value).expandtabs().replace(" ", "_")
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def __init__(self, signal_names, *, vcd_file, gtkw_file=None, traces=()):
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if isinstance(vcd_file, str):
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vcd_file = open(vcd_file, "wt")
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if isinstance(gtkw_file, str):
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gtkw_file = open(gtkw_file, "wt")
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self.vcd_vars = SignalDict()
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self.vcd_file = vcd_file
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self.vcd_writer = vcd_file and VCDWriter(self.vcd_file,
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timescale="100 ps", comment="Generated by nMigen")
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self.gtkw_names = SignalDict()
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self.gtkw_file = gtkw_file
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self.gtkw_save = gtkw_file and GTKWSave(self.gtkw_file)
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self.traces = []
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trace_names = SignalDict()
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for trace in traces:
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if trace not in signal_names:
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trace_names[trace] = trace.name
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self.traces.append(trace)
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if self.vcd_writer is None:
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return
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for signal, names in itertools.chain(signal_names.items(), trace_names.items()):
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if signal.decoder:
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var_type = "string"
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var_size = 1
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var_init = self.decode_to_vcd(signal, signal.reset)
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else:
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var_type = "wire"
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var_size = signal.width
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var_init = signal.reset
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for (*var_scope, var_name) in names:
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suffix = None
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while True:
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try:
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if suffix is None:
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var_name_suffix = var_name
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else:
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var_name_suffix = "{}${}".format(var_name, suffix)
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vcd_var = self.vcd_writer.register_var(
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scope=var_scope, name=var_name_suffix,
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var_type=var_type, size=var_size, init=var_init)
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break
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except KeyError:
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suffix = (suffix or 0) + 1
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if signal not in self.vcd_vars:
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self.vcd_vars[signal] = set()
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self.vcd_vars[signal].add(vcd_var)
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if signal not in self.gtkw_names:
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self.gtkw_names[signal] = (*var_scope, var_name_suffix)
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def update(self, timestamp, signal, value):
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if signal not in self.vcd_vars:
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return
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vcd_timestamp = self.timestamp_to_vcd(timestamp)
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if signal.decoder:
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var_value = self.decode_to_vcd(signal, value)
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else:
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var_value = value
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for vcd_var in self.vcd_vars[signal]:
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self.vcd_writer.change(vcd_var, vcd_timestamp, var_value)
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def close(self, timestamp):
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if self.vcd_writer is not None:
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self.vcd_writer.close(self.timestamp_to_vcd(timestamp))
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if self.gtkw_save is not None:
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self.gtkw_save.dumpfile(self.vcd_file.name)
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self.gtkw_save.dumpfile_size(self.vcd_file.tell())
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self.gtkw_save.treeopen("top")
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for signal in self.traces:
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if len(signal) > 1 and not signal.decoder:
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suffix = "[{}:0]".format(len(signal) - 1)
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else:
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suffix = ""
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self.gtkw_save.trace(".".join(self.gtkw_names[signal]) + suffix)
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if self.vcd_file is not None:
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self.vcd_file.close()
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if self.gtkw_file is not None:
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self.gtkw_file.close()
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class _Process:
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__slots__ = ("runnable", "passive")
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def reset(self):
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raise NotImplementedError # :nocov:
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def run(self):
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raise NotImplementedError # :nocov:
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@property
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def name(self):
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raise NotImplementedError # :nocov:
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class _SignalState:
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__slots__ = ("signal", "curr", "next", "waiters", "pending")
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def __init__(self, signal, pending):
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self.signal = signal
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self.pending = pending
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self.waiters = dict()
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self.reset()
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def reset(self):
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self.curr = self.next = self.signal.reset
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def set(self, value):
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if self.next == value:
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return
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self.next = value
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self.pending.add(self)
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def wait(self, task, *, trigger=None):
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assert task not in self.waiters
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self.waiters[task] = trigger
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def commit(self):
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if self.curr == self.next:
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return False
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self.curr = self.next
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return True
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def wakeup(self):
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awoken_any = False
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for process, trigger in self.waiters.items():
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if trigger is None or trigger == self.curr:
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process.runnable = awoken_any = True
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return awoken_any
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class _SimulatorState:
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def __init__(self):
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self.signals = SignalDict()
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self.pending = set()
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self.timestamp = 0.0
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self.deadlines = dict()
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self.waveform_writer = None
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def reset(self):
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for signal_state in self.signals.values():
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signal_state.reset()
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self.pending.clear()
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self.timestamp = 0.0
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self.deadlines.clear()
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def for_signal(self, signal):
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try:
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return self.signals[signal]
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except KeyError:
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signal_state = _SignalState(signal, self.pending)
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self.signals[signal] = signal_state
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return signal_state
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def commit(self):
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awoken_any = False
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for signal_state in self.pending:
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if signal_state.commit():
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if signal_state.wakeup():
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awoken_any = True
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if self.waveform_writer is not None:
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self.waveform_writer.update(self.timestamp,
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signal_state.signal, signal_state.curr)
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return awoken_any
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def advance(self):
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nearest_processes = set()
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nearest_deadline = None
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for process, deadline in self.deadlines.items():
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if deadline is None:
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if nearest_deadline is not None:
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nearest_processes.clear()
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nearest_processes.add(process)
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nearest_deadline = self.timestamp
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break
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elif nearest_deadline is None or deadline <= nearest_deadline:
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assert deadline >= self.timestamp
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if nearest_deadline is not None and deadline < nearest_deadline:
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nearest_processes.clear()
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nearest_processes.add(process)
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nearest_deadline = deadline
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if not nearest_processes:
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return False
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for process in nearest_processes:
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process.runnable = True
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del self.deadlines[process]
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self.timestamp = nearest_deadline
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return True
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def start_waveform(self, waveform_writer):
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if self.timestamp != 0.0:
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raise ValueError("Cannot start writing waveforms after advancing simulation time")
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if self.waveform_writer is not None:
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raise ValueError("Already writing waveforms to {!r}"
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.format(self.waveform_writer))
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self.waveform_writer = waveform_writer
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def finish_waveform(self):
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if self.waveform_writer is None:
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return
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self.waveform_writer.close(self.timestamp)
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self.waveform_writer = None
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class _EvalContext:
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__slots__ = ("state", "indexes", "slots")
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def __init__(self, state):
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self.state = state
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self.indexes = SignalDict()
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self.slots = []
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def get_signal(self, signal):
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try:
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return self.indexes[signal]
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except KeyError:
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index = len(self.slots)
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self.slots.append(self.state.for_signal(signal))
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self.indexes[signal] = index
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return index
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def get_in_signal(self, signal, *, trigger=None):
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index = self.get_signal(signal)
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self.slots[index].waiters[self] = trigger
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return index
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def get_out_signal(self, signal):
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return self.get_signal(signal)
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class _Emitter:
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def __init__(self):
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self._buffer = []
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self._suffix = 0
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self._level = 0
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def append(self, code):
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self._buffer.append(" " * self._level)
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self._buffer.append(code)
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self._buffer.append("\n")
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@contextmanager
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def indent(self):
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self._level += 1
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yield
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self._level -= 1
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def flush(self, indent=""):
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code = "".join(self._buffer)
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self._buffer.clear()
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return code
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def gen_var(self, prefix):
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name = f"{prefix}_{self._suffix}"
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self._suffix += 1
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return name
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def def_var(self, prefix, value):
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name = self.gen_var(prefix)
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self.append(f"{name} = {value}")
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return name
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class _Compiler:
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def __init__(self, context, emitter):
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self.context = context
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self.emitter = emitter
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class _ValueCompiler(ValueVisitor, _Compiler):
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helpers = {
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"sign": lambda value, sign: value | sign if value & sign else value,
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"zdiv": lambda lhs, rhs: 0 if rhs == 0 else lhs // rhs,
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}
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def on_ClockSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_ResetSignal(self, value):
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raise NotImplementedError # :nocov:
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def on_Record(self, value):
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return self(Cat(value.fields.values()))
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def on_AnyConst(self, value):
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raise NotImplementedError # :nocov:
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def on_AnySeq(self, value):
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raise NotImplementedError # :nocov:
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def on_Sample(self, value):
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raise NotImplementedError # :nocov:
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def on_Initial(self, value):
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raise NotImplementedError # :nocov:
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class _RHSValueCompiler(_ValueCompiler):
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def __init__(self, context, emitter, *, mode, inputs=None):
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super().__init__(context, emitter)
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assert mode in ("curr", "next")
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self.mode = mode
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# If not None, `inputs` gets populated with RHS signals.
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self.inputs = inputs
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def on_Const(self, value):
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return f"{value.value}"
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def on_Signal(self, value):
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if self.inputs is not None:
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self.inputs.add(value)
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if self.mode == "curr":
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return f"slots[{self.context.get_signal(value)}].{self.mode}"
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else:
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return f"next_{self.context.get_signal(value)}"
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def on_Operator(self, value):
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def mask(value):
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value_mask = (1 << len(value)) - 1
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return f"({self(value)} & {value_mask})"
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def sign(value):
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if value.shape().signed:
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return f"sign({mask(value)}, {-1 << (len(value) - 1)})"
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else: # unsigned
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return mask(value)
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if len(value.operands) == 1:
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arg, = value.operands
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if value.operator == "~":
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return f"(~{self(arg)})"
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if value.operator == "-":
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return f"(-{self(arg)})"
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if value.operator == "b":
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return f"bool({mask(arg)})"
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if value.operator == "r|":
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return f"({mask(arg)} != 0)"
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if value.operator == "r&":
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return f"({mask(arg)} == {(1 << len(arg)) - 1})"
|
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if value.operator == "r^":
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# Believe it or not, this is the fastest way to compute a sideways XOR in Python.
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return f"(format({mask(arg)}, 'b').count('1') % 2)"
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if value.operator in ("u", "s"):
|
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# These operators don't change the bit pattern, only its interpretation.
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return self(arg)
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elif len(value.operands) == 2:
|
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lhs, rhs = value.operands
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lhs_mask = (1 << len(lhs)) - 1
|
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rhs_mask = (1 << len(rhs)) - 1
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if value.operator == "+":
|
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return f"({sign(lhs)} + {sign(rhs)})"
|
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if value.operator == "-":
|
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return f"({sign(lhs)} - {sign(rhs)})"
|
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if value.operator == "*":
|
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return f"({sign(lhs)} * {sign(rhs)})"
|
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if value.operator == "//":
|
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return f"zdiv({sign(lhs)}, {sign(rhs)})"
|
|
if value.operator == "&":
|
|
return f"({self(lhs)} & {self(rhs)})"
|
|
if value.operator == "|":
|
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return f"({self(lhs)} | {self(rhs)})"
|
|
if value.operator == "^":
|
|
return f"({self(lhs)} ^ {self(rhs)})"
|
|
if value.operator == "<<":
|
|
return f"({sign(lhs)} << {sign(rhs)})"
|
|
if value.operator == ">>":
|
|
return f"({sign(lhs)} >> {sign(rhs)})"
|
|
if value.operator == "==":
|
|
return f"({sign(lhs)} == {sign(rhs)})"
|
|
if value.operator == "!=":
|
|
return f"({sign(lhs)} != {sign(rhs)})"
|
|
if value.operator == "<":
|
|
return f"({sign(lhs)} < {sign(rhs)})"
|
|
if value.operator == "<=":
|
|
return f"({sign(lhs)} <= {sign(rhs)})"
|
|
if value.operator == ">":
|
|
return f"({sign(lhs)} > {sign(rhs)})"
|
|
if value.operator == ">=":
|
|
return f"({sign(lhs)} >= {sign(rhs)})"
|
|
elif len(value.operands) == 3:
|
|
if value.operator == "m":
|
|
sel, val1, val0 = value.operands
|
|
return f"({self(val1)} if {self(sel)} else {self(val0)})"
|
|
raise NotImplementedError("Operator '{}' not implemented".format(value.operator)) # :nocov:
|
|
|
|
def on_Slice(self, value):
|
|
return f"(({self(value.value)} >> {value.start}) & {(1 << len(value)) - 1})"
|
|
|
|
def on_Part(self, value):
|
|
offset_mask = (1 << len(value.offset)) - 1
|
|
offset = f"(({self(value.offset)} & {offset_mask}) * {value.stride})"
|
|
return f"({self(value.value)} >> {offset} & " \
|
|
f"{(1 << value.width) - 1})"
|
|
|
|
def on_Cat(self, value):
|
|
gen_parts = []
|
|
offset = 0
|
|
for part in value.parts:
|
|
part_mask = (1 << len(part)) - 1
|
|
gen_parts.append(f"(({self(part)} & {part_mask}) << {offset})")
|
|
offset += len(part)
|
|
if gen_parts:
|
|
return f"({' | '.join(gen_parts)})"
|
|
return f"0"
|
|
|
|
def on_Repl(self, value):
|
|
part_mask = (1 << len(value.value)) - 1
|
|
gen_part = self.emitter.def_var("repl", f"{self(value.value)} & {part_mask}")
|
|
gen_parts = []
|
|
offset = 0
|
|
for _ in range(value.count):
|
|
gen_parts.append(f"({gen_part} << {offset})")
|
|
offset += len(value.value)
|
|
if gen_parts:
|
|
return f"({' | '.join(gen_parts)})"
|
|
return f"0"
|
|
|
|
def on_ArrayProxy(self, value):
|
|
index_mask = (1 << len(value.index)) - 1
|
|
gen_index = self.emitter.def_var("rhs_index", f"{self(value.index)} & {index_mask}")
|
|
gen_value = self.emitter.gen_var("rhs_proxy")
|
|
if value.elems:
|
|
gen_elems = []
|
|
for index, elem in enumerate(value.elems):
|
|
if index == 0:
|
|
self.emitter.append(f"if {gen_index} == {index}:")
|
|
else:
|
|
self.emitter.append(f"elif {gen_index} == {index}:")
|
|
with self.emitter.indent():
|
|
self.emitter.append(f"{gen_value} = {self(elem)}")
|
|
self.emitter.append(f"else:")
|
|
with self.emitter.indent():
|
|
self.emitter.append(f"{gen_value} = {self(value.elems[-1])}")
|
|
return gen_value
|
|
else:
|
|
return f"0"
|
|
|
|
@classmethod
|
|
def compile(cls, context, value, *, mode, inputs=None):
|
|
emitter = _Emitter()
|
|
compiler = cls(context, emitter, mode=mode, inputs=inputs)
|
|
emitter.append(f"result = {compiler(value)}")
|
|
return emitter.flush()
|
|
|
|
|
|
class _LHSValueCompiler(_ValueCompiler):
|
|
def __init__(self, context, emitter, *, rhs, outputs=None):
|
|
super().__init__(context, emitter)
|
|
# `rrhs` is used to translate rvalues that are syntactically a part of an lvalue, e.g.
|
|
# the offset of a Part.
|
|
self.rrhs = rhs
|
|
# `lrhs` is used to translate the read part of a read-modify-write cycle during partial
|
|
# update of an lvalue.
|
|
self.lrhs = _RHSValueCompiler(context, emitter, mode="next", inputs=None)
|
|
# If not None, `outputs` gets populated with signals on LHS.
|
|
self.outputs = outputs
|
|
|
|
def on_Const(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
def on_Signal(self, value):
|
|
if self.outputs is not None:
|
|
self.outputs.add(value)
|
|
|
|
def gen(arg):
|
|
value_mask = (1 << len(value)) - 1
|
|
if value.shape().signed:
|
|
value_sign = f"sign({arg} & {value_mask}, {-1 << (len(value) - 1)})"
|
|
else: # unsigned
|
|
value_sign = f"{arg} & {value_mask}"
|
|
self.emitter.append(f"next_{self.context.get_out_signal(value)} = {value_sign}")
|
|
return gen
|
|
|
|
def on_Operator(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
def on_Slice(self, value):
|
|
def gen(arg):
|
|
width_mask = (1 << (value.stop - value.start)) - 1
|
|
self(value.value)(f"({self.lrhs(value.value)} & " \
|
|
f"{~(width_mask << value.start)} | " \
|
|
f"(({arg} & {width_mask}) << {value.start}))")
|
|
return gen
|
|
|
|
def on_Part(self, value):
|
|
def gen(arg):
|
|
width_mask = (1 << value.width) - 1
|
|
offset_mask = (1 << len(value.offset)) - 1
|
|
offset = f"(({self.rrhs(value.offset)} & {offset_mask}) * {value.stride})"
|
|
self(value.value)(f"({self.lrhs(value.value)} & " \
|
|
f"~({width_mask} << {offset}) | " \
|
|
f"(({arg} & {width_mask}) << {offset}))")
|
|
return gen
|
|
|
|
def on_Cat(self, value):
|
|
def gen(arg):
|
|
gen_arg = self.emitter.def_var("cat", arg)
|
|
gen_parts = []
|
|
offset = 0
|
|
for part in value.parts:
|
|
part_mask = (1 << len(part)) - 1
|
|
self(part)(f"(({gen_arg} >> {offset}) & {part_mask})")
|
|
offset += len(part)
|
|
return gen
|
|
|
|
def on_Repl(self, value):
|
|
raise TypeError # :nocov:
|
|
|
|
def on_ArrayProxy(self, value):
|
|
def gen(arg):
|
|
index_mask = (1 << len(value.index)) - 1
|
|
gen_index = self.emitter.def_var("index", f"{self.rrhs(value.index)} & {index_mask}")
|
|
if value.elems:
|
|
gen_elems = []
|
|
for index, elem in enumerate(value.elems):
|
|
if index == 0:
|
|
self.emitter.append(f"if {gen_index} == {index}:")
|
|
else:
|
|
self.emitter.append(f"elif {gen_index} == {index}:")
|
|
with self.emitter.indent():
|
|
self(elem)(arg)
|
|
self.emitter.append(f"else:")
|
|
with self.emitter.indent():
|
|
self(value.elems[-1])(arg)
|
|
else:
|
|
self.emitter.append(f"pass")
|
|
return gen
|
|
|
|
@classmethod
|
|
def compile(cls, context, stmt, *, inputs=None, outputs=None):
|
|
emitter = _Emitter()
|
|
compiler = cls(context, emitter, inputs=inputs, outputs=outputs)
|
|
compiler(stmt)
|
|
return emitter.flush()
|
|
|
|
|
|
class _StatementCompiler(StatementVisitor, _Compiler):
|
|
def __init__(self, context, emitter, *, inputs=None, outputs=None):
|
|
super().__init__(context, emitter)
|
|
self.rhs = _RHSValueCompiler(context, emitter, mode="curr", inputs=inputs)
|
|
self.lhs = _LHSValueCompiler(context, emitter, rhs=self.rhs, outputs=outputs)
|
|
|
|
def on_statements(self, stmts):
|
|
for stmt in stmts:
|
|
self(stmt)
|
|
if not stmts:
|
|
self.emitter.append("pass")
|
|
|
|
def on_Assign(self, stmt):
|
|
return self.lhs(stmt.lhs)(self.rhs(stmt.rhs))
|
|
|
|
def on_Switch(self, stmt):
|
|
gen_test = self.emitter.def_var("test",
|
|
f"{self.rhs(stmt.test)} & {(1 << len(stmt.test)) - 1}")
|
|
for index, (patterns, stmts) in enumerate(stmt.cases.items()):
|
|
gen_checks = []
|
|
if not patterns:
|
|
gen_checks.append(f"True")
|
|
else:
|
|
for pattern in patterns:
|
|
if "-" in pattern:
|
|
mask = int("".join("0" if b == "-" else "1" for b in pattern), 2)
|
|
value = int("".join("0" if b == "-" else b for b in pattern), 2)
|
|
gen_checks.append(f"({gen_test} & {mask}) == {value}")
|
|
else:
|
|
value = int(pattern, 2)
|
|
gen_checks.append(f"{gen_test} == {value}")
|
|
if index == 0:
|
|
self.emitter.append(f"if {' or '.join(gen_checks)}:")
|
|
else:
|
|
self.emitter.append(f"elif {' or '.join(gen_checks)}:")
|
|
with self.emitter.indent():
|
|
self(stmts)
|
|
|
|
def on_Assert(self, stmt):
|
|
raise NotImplementedError # :nocov:
|
|
|
|
def on_Assume(self, stmt):
|
|
raise NotImplementedError # :nocov:
|
|
|
|
def on_Cover(self, stmt):
|
|
raise NotImplementedError # :nocov:
|
|
|
|
@classmethod
|
|
def compile(cls, context, stmt, *, inputs=None, outputs=None):
|
|
output_indexes = [context.get_signal(signal) for signal in stmt._lhs_signals()]
|
|
emitter = _Emitter()
|
|
for signal_index in output_indexes:
|
|
emitter.append(f"next_{signal_index} = slots[{signal_index}].next")
|
|
compiler = cls(context, emitter, inputs=inputs, outputs=outputs)
|
|
compiler(stmt)
|
|
for signal_index in output_indexes:
|
|
emitter.append(f"slots[{signal_index}].set(next_{signal_index})")
|
|
return emitter.flush()
|
|
|
|
|
|
class _CompiledProcess(_Process):
|
|
__slots__ = ("context", "comb", "name", "run")
|
|
|
|
def __init__(self, state, *, comb, name):
|
|
self.context = _EvalContext(state)
|
|
self.comb = comb
|
|
self.name = name
|
|
self.run = None # set by _FragmentCompiler
|
|
self.reset()
|
|
|
|
def reset(self):
|
|
self.runnable = self.comb
|
|
self.passive = True
|
|
|
|
|
|
class _FragmentCompiler:
|
|
def __init__(self, state, signal_names):
|
|
self.state = state
|
|
self.signal_names = signal_names
|
|
|
|
def __call__(self, fragment, *, hierarchy=("top",)):
|
|
processes = set()
|
|
|
|
def add_signal_name(signal):
|
|
hierarchical_signal_name = (*hierarchy, signal.name)
|
|
if signal not in self.signal_names:
|
|
self.signal_names[signal] = {hierarchical_signal_name}
|
|
else:
|
|
self.signal_names[signal].add(hierarchical_signal_name)
|
|
|
|
for domain_name, domain_signals in fragment.drivers.items():
|
|
domain_stmts = LHSGroupFilter(domain_signals)(fragment.statements)
|
|
domain_process = _CompiledProcess(self.state, comb=domain_name is None,
|
|
name=".".join((*hierarchy, "<{}>".format(domain_name or "comb"))))
|
|
|
|
emitter = _Emitter()
|
|
emitter.append(f"def run():")
|
|
emitter._level += 1
|
|
|
|
if domain_name is None:
|
|
for signal in domain_signals:
|
|
signal_index = domain_process.context.get_signal(signal)
|
|
emitter.append(f"next_{signal_index} = {signal.reset}")
|
|
|
|
inputs = SignalSet()
|
|
_StatementCompiler(domain_process.context, emitter, inputs=inputs)(domain_stmts)
|
|
|
|
for input in inputs:
|
|
self.state.for_signal(input).wait(domain_process)
|
|
|
|
else:
|
|
domain = fragment.domains[domain_name]
|
|
add_signal_name(domain.clk)
|
|
if domain.rst is not None:
|
|
add_signal_name(domain.rst)
|
|
|
|
clk_trigger = 1 if domain.clk_edge == "pos" else 0
|
|
self.state.for_signal(domain.clk).wait(domain_process, trigger=clk_trigger)
|
|
if domain.rst is not None and domain.async_reset:
|
|
rst_trigger = 1
|
|
self.state.for_signal(domain.rst).wait(domain_process, trigger=rst_trigger)
|
|
|
|
gen_asserts = []
|
|
clk_index = domain_process.context.get_signal(domain.clk)
|
|
gen_asserts.append(f"slots[{clk_index}].curr == {clk_trigger}")
|
|
if domain.rst is not None and domain.async_reset:
|
|
rst_index = domain_process.context.get_signal(domain.rst)
|
|
gen_asserts.append(f"slots[{rst_index}].curr == {rst_trigger}")
|
|
emitter.append(f"assert {' or '.join(gen_asserts)}")
|
|
|
|
for signal in domain_signals:
|
|
signal_index = domain_process.context.get_signal(signal)
|
|
emitter.append(f"next_{signal_index} = slots[{signal_index}].next")
|
|
|
|
_StatementCompiler(domain_process.context, emitter)(domain_stmts)
|
|
|
|
for signal in domain_signals:
|
|
signal_index = domain_process.context.get_signal(signal)
|
|
emitter.append(f"slots[{signal_index}].set(next_{signal_index})")
|
|
|
|
# There shouldn't be any exceptions raised by the generated code, but if there are
|
|
# (almost certainly due to a bug in the code generator), use this environment variable
|
|
# to make backtraces useful.
|
|
code = emitter.flush()
|
|
if os.getenv("NMIGEN_pysim_dump"):
|
|
file = tempfile.NamedTemporaryFile("w", prefix="nmigen_pysim_", delete=False)
|
|
file.write(code)
|
|
filename = file.name
|
|
else:
|
|
filename = "<string>"
|
|
|
|
exec_locals = {"slots": domain_process.context.slots, **_ValueCompiler.helpers}
|
|
exec(compile(code, filename, "exec"), exec_locals)
|
|
domain_process.run = exec_locals["run"]
|
|
|
|
processes.add(domain_process)
|
|
|
|
for used_signal in domain_process.context.indexes:
|
|
add_signal_name(used_signal)
|
|
|
|
for subfragment_index, (subfragment, subfragment_name) in enumerate(fragment.subfragments):
|
|
if subfragment_name is None:
|
|
subfragment_name = "U${}".format(subfragment_index)
|
|
processes.update(self(subfragment, hierarchy=(*hierarchy, subfragment_name)))
|
|
|
|
return processes
|
|
|
|
|
|
class _CoroutineProcess(_Process):
|
|
def __init__(self, state, domains, constructor, *, default_cmd=None):
|
|
self.state = state
|
|
self.domains = domains
|
|
self.constructor = constructor
|
|
self.default_cmd = default_cmd
|
|
self.reset()
|
|
|
|
def reset(self):
|
|
self.runnable = True
|
|
self.passive = False
|
|
self.coroutine = self.constructor()
|
|
self.eval_context = _EvalContext(self.state)
|
|
self.exec_locals = {
|
|
"slots": self.eval_context.slots,
|
|
"result": None,
|
|
**_ValueCompiler.helpers
|
|
}
|
|
self.waits_on = set()
|
|
|
|
@property
|
|
def name(self):
|
|
coroutine = self.coroutine
|
|
while coroutine.gi_yieldfrom is not None:
|
|
coroutine = coroutine.gi_yieldfrom
|
|
if inspect.isgenerator(coroutine):
|
|
frame = coroutine.gi_frame
|
|
if inspect.iscoroutine(coroutine):
|
|
frame = coroutine.cr_frame
|
|
return "{}:{}".format(inspect.getfile(frame), inspect.getlineno(frame))
|
|
|
|
def get_in_signal(self, signal, *, trigger=None):
|
|
signal_state = self.state.for_signal(signal)
|
|
assert self not in signal_state.waiters
|
|
signal_state.waiters[self] = trigger
|
|
self.waits_on.add(signal_state)
|
|
return signal_state
|
|
|
|
def run(self):
|
|
if self.coroutine is None:
|
|
return
|
|
|
|
if self.waits_on:
|
|
for signal_state in self.waits_on:
|
|
del signal_state.waiters[self]
|
|
self.waits_on.clear()
|
|
|
|
response = None
|
|
while True:
|
|
try:
|
|
command = self.coroutine.send(response)
|
|
if command is None:
|
|
command = self.default_cmd
|
|
response = None
|
|
|
|
if isinstance(command, Value):
|
|
exec(_RHSValueCompiler.compile(self.eval_context, command, mode="curr"),
|
|
self.exec_locals)
|
|
response = Const.normalize(self.exec_locals["result"], command.shape())
|
|
|
|
elif isinstance(command, Statement):
|
|
exec(_StatementCompiler.compile(self.eval_context, command),
|
|
self.exec_locals)
|
|
|
|
elif type(command) is Tick:
|
|
domain = command.domain
|
|
if isinstance(domain, ClockDomain):
|
|
pass
|
|
elif domain in self.domains:
|
|
domain = self.domains[domain]
|
|
else:
|
|
raise NameError("Received command {!r} that refers to a nonexistent "
|
|
"domain {!r} from process {!r}"
|
|
.format(command, command.domain, self.name))
|
|
self.get_in_signal(domain.clk, trigger=1 if domain.clk_edge == "pos" else 0)
|
|
if domain.rst is not None and domain.async_reset:
|
|
self.get_in_signal(domain.rst, trigger=1)
|
|
return
|
|
|
|
elif type(command) is Settle:
|
|
self.state.deadlines[self] = None
|
|
return
|
|
|
|
elif type(command) is Delay:
|
|
if command.interval is None:
|
|
self.state.deadlines[self] = None
|
|
else:
|
|
self.state.deadlines[self] = self.state.timestamp + command.interval
|
|
return
|
|
|
|
elif type(command) is Passive:
|
|
self.passive = True
|
|
|
|
elif type(command) is Active:
|
|
self.passive = False
|
|
|
|
elif command is None: # only possible if self.default_cmd is None
|
|
raise TypeError("Received default command from process {!r} that was added "
|
|
"with add_process(); did you mean to add this process with "
|
|
"add_sync_process() instead?"
|
|
.format(self.name))
|
|
|
|
else:
|
|
raise TypeError("Received unsupported command {!r} from process {!r}"
|
|
.format(command, self.name))
|
|
|
|
except StopIteration:
|
|
self.passive = True
|
|
self.coroutine = None
|
|
return
|
|
|
|
except Exception as exn:
|
|
self.coroutine.throw(exn)
|
|
|
|
|
|
class _WaveformContextManager:
|
|
def __init__(self, state, waveform_writer):
|
|
self._state = state
|
|
self._waveform_writer = waveform_writer
|
|
|
|
def __enter__(self):
|
|
try:
|
|
self._state.start_waveform(self._waveform_writer)
|
|
except:
|
|
self._waveform_writer.close(0)
|
|
raise
|
|
|
|
def __exit__(self, *args):
|
|
self._state.finish_waveform()
|
|
|
|
|
|
class Simulator:
|
|
def __init__(self, fragment, **kwargs):
|
|
self._state = _SimulatorState()
|
|
self._signal_names = SignalDict()
|
|
self._fragment = Fragment.get(fragment, platform=None).prepare()
|
|
self._processes = _FragmentCompiler(self._state, self._signal_names)(self._fragment)
|
|
if kwargs: # :nocov:
|
|
# TODO(nmigen-0.3): remove
|
|
self._state.start_waveform(_VCDWaveformWriter(self._signal_names, **kwargs))
|
|
self._clocked = set()
|
|
|
|
def _check_process(self, process):
|
|
if not (inspect.isgeneratorfunction(process) or inspect.iscoroutinefunction(process)):
|
|
if inspect.isgenerator(process) or inspect.iscoroutine(process):
|
|
warnings.warn("instead of generators, use generator functions as processes; "
|
|
"this allows the simulator to be repeatedly reset",
|
|
DeprecationWarning, stacklevel=3)
|
|
def wrapper():
|
|
yield from process
|
|
return wrapper
|
|
else:
|
|
raise TypeError("Cannot add a process {!r} because it is not a generator function"
|
|
.format(process))
|
|
return process
|
|
|
|
def _add_coroutine_process(self, process, *, default_cmd):
|
|
self._processes.add(_CoroutineProcess(self._state, self._fragment.domains, process,
|
|
default_cmd=default_cmd))
|
|
|
|
def add_process(self, process):
|
|
process = self._check_process(process)
|
|
def wrapper():
|
|
# Only start a bench process after comb settling, so that the reset values are correct.
|
|
yield Settle()
|
|
yield from process()
|
|
self._add_coroutine_process(wrapper, default_cmd=None)
|
|
|
|
def add_sync_process(self, process, *, domain="sync"):
|
|
process = self._check_process(process)
|
|
def wrapper():
|
|
# Only start a sync process after the first clock edge (or reset edge, if the domain
|
|
# uses an asynchronous reset). This matches the behavior of synchronous FFs.
|
|
yield Tick(domain)
|
|
yield from process()
|
|
return self._add_coroutine_process(wrapper, default_cmd=Tick(domain))
|
|
|
|
def add_clock(self, period, *, phase=None, domain="sync", if_exists=False):
|
|
"""Add a clock process.
|
|
|
|
Adds a process that drives the clock signal of ``domain`` at a 50% duty cycle.
|
|
|
|
Arguments
|
|
---------
|
|
period : float
|
|
Clock period. The process will toggle the ``domain`` clock signal every ``period / 2``
|
|
seconds.
|
|
phase : None or float
|
|
Clock phase. The process will wait ``phase`` seconds before the first clock transition.
|
|
If not specified, defaults to ``period / 2``.
|
|
domain : str or ClockDomain
|
|
Driven clock domain. If specified as a string, the domain with that name is looked up
|
|
in the root fragment of the simulation.
|
|
if_exists : bool
|
|
If ``False`` (the default), raise an error if the driven domain is specified as
|
|
a string and the root fragment does not have such a domain. If ``True``, do nothing
|
|
in this case.
|
|
"""
|
|
if isinstance(domain, ClockDomain):
|
|
pass
|
|
elif domain in self._fragment.domains:
|
|
domain = self._fragment.domains[domain]
|
|
elif if_exists:
|
|
return
|
|
else:
|
|
raise ValueError("Domain {!r} is not present in simulation"
|
|
.format(domain))
|
|
if domain in self._clocked:
|
|
raise ValueError("Domain {!r} already has a clock driving it"
|
|
.format(domain.name))
|
|
|
|
half_period = period / 2
|
|
if phase is None:
|
|
# By default, delay the first edge by half period. This causes any synchronous activity
|
|
# to happen at a non-zero time, distinguishing it from the reset values in the waveform
|
|
# viewer.
|
|
phase = half_period
|
|
def clk_process():
|
|
yield Passive()
|
|
yield Delay(phase)
|
|
# Behave correctly if the process is added after the clock signal is manipulated, or if
|
|
# its reset state is high.
|
|
initial = (yield domain.clk)
|
|
while True:
|
|
yield domain.clk.eq(~initial)
|
|
yield Delay(half_period)
|
|
yield domain.clk.eq(initial)
|
|
yield Delay(half_period)
|
|
self._add_coroutine_process(clk_process, default_cmd=None)
|
|
self._clocked.add(domain)
|
|
|
|
def reset(self):
|
|
"""Reset the simulation.
|
|
|
|
Assign the reset value to every signal in the simulation, and restart every user process.
|
|
"""
|
|
self._state.reset()
|
|
for process in self._processes:
|
|
process.reset()
|
|
|
|
def _delta(self):
|
|
"""Perform a delta cycle.
|
|
|
|
Performs the two phases of a delta cycle:
|
|
1. run and suspend every non-waiting process once, queueing signal changes;
|
|
2. commit every queued signal change, waking up any waiting process.
|
|
"""
|
|
for process in self._processes:
|
|
if process.runnable:
|
|
process.runnable = False
|
|
process.run()
|
|
|
|
return self._state.commit()
|
|
|
|
def _settle(self):
|
|
"""Settle the simulation.
|
|
|
|
Run every process and commit changes until a fixed point is reached. If there is
|
|
an unstable combinatorial loop, this function will never return.
|
|
"""
|
|
while self._delta():
|
|
pass
|
|
|
|
def step(self):
|
|
"""Step the simulation.
|
|
|
|
Run every process and commit changes until a fixed point is reached, then advance time
|
|
to the closest deadline (if any). If there is an unstable combinatorial loop,
|
|
this function will never return.
|
|
|
|
Returns ``True`` if there are any active processes, ``False`` otherwise.
|
|
"""
|
|
self._settle()
|
|
self._state.advance()
|
|
return any(not process.passive for process in self._processes)
|
|
|
|
def run(self):
|
|
"""Run the simulation while any processes are active.
|
|
|
|
Processes added with :meth:`add_process` and :meth:`add_sync_process` are initially active,
|
|
and may change their status using the ``yield Passive()`` and ``yield Active()`` commands.
|
|
Processes compiled from HDL and added with :meth:`add_clock` are always passive.
|
|
"""
|
|
while self.step():
|
|
pass
|
|
|
|
def run_until(self, deadline, *, run_passive=False):
|
|
"""Run the simulation until it advances to ``deadline``.
|
|
|
|
If ``run_passive`` is ``False``, the simulation also stops when there are no active
|
|
processes, similar to :meth:`run`. Otherwise, the simulation will stop only after it
|
|
advances to or past ``deadline``.
|
|
|
|
If the simulation stops advancing, this function will never return.
|
|
"""
|
|
assert self._state.timestamp <= deadline
|
|
while (self.step() or run_passive) and self._state.timestamp < deadline:
|
|
pass
|
|
|
|
def write_vcd(self, vcd_file, gtkw_file=None, *, traces=()):
|
|
"""Write waveforms to a Value Change Dump file, optionally populating a GTKWave save file.
|
|
|
|
This method returns a context manager. It can be used as: ::
|
|
|
|
sim = Simulator(frag)
|
|
sim.add_clock(1e-6)
|
|
with sim.write_vcd("dump.vcd", "dump.gtkw"):
|
|
sim.run_until(1e-3)
|
|
|
|
Arguments
|
|
---------
|
|
vcd_file : str or file-like object
|
|
Verilog Value Change Dump file or filename.
|
|
gtkw_file : str or file-like object
|
|
GTKWave save file or filename.
|
|
traces : iterable of Signal
|
|
Signals to display traces for.
|
|
"""
|
|
waveform_writer = _VCDWaveformWriter(self._signal_names,
|
|
vcd_file=vcd_file, gtkw_file=gtkw_file, traces=traces)
|
|
return _WaveformContextManager(self._state, waveform_writer)
|
|
|
|
# TODO(nmigen-0.3): remove
|
|
@deprecated("instead of `with Simulator(fragment, ...) as sim:`, use "
|
|
"`sim = Simulator(fragment); with sim.write_vcd(...):`")
|
|
def __enter__(self): # :nocov:
|
|
return self
|
|
|
|
# TODO(nmigen-0.3): remove
|
|
def __exit__(self, *args): # :nocov:
|
|
self._state.finish_waveform()
|