29 lines
1.7 KiB
Markdown
29 lines
1.7 KiB
Markdown
# RISC-V Instructions
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Refer to the table below for the instructions currently supported. At the time of writing, it covers the instructions in the RV32I base ISA except FENCE, ECALL and EBREAK, as well as the RV32M extension\*.
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| Instruction type | Instructions |
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| --- | --- |
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| U-type | lui, auipc |
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| UJ-type | jal |
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| I-type | jalr, lb, lh, lw, lbu, lhu, addi, slti, sltiu, xori, ori, andi |
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| SB-type | beq, bne, blt, bge, bltu, bgeu |
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| S-type | sb, sh, sw |
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| I-type (shift variation) | slli, srli, srai |
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| R-type | add, sub, sll, slt, sltu, xor, srl, sra, or, and, mul, mulh, mulhsu, mulhu, div, divu, rem, remu |
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\* Due to limitations with modern solvers, they are sometimes unable to verify assertions involving multiplication and/or division; therefore, the core under test is expected to implement alternative operations for the RV32M extensions for the purposes of formal verification only, replacing multiplication/division operations with addition/subtraction and XORing with selected bitmasks.
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## Caveats
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At the time of writing, the set of instructions supported in this port of riscv-formal is a mere subset of those supported in the original riscv-formal; for example, compressed instructions and 64-bit ISAs/extensions are not supported. Also note that the original riscv-formal contains tunable parameters that have been fixed to certain values in this translation:
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| Parameter from riscv-formal | Fixed value in riscv-formal-nmigen |
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| --- | --- |
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| `RISCV_FORMAL_ILEN` | 32 |
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| `RISCV_FORMAL_XLEN` | 32 |
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| `RISCV_FORMAL_CSR_MISA` | undefined |
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| `RISCV_FORMAL_COMPRESSED` | undefined |
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| `RISCV_FORMAL_ALIGNED_MEM` | undefined |
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| `RISCV_FORMAL_ALTOPS` | defined |
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