295 lines
10 KiB
Python
295 lines
10 KiB
Python
from nmigen import *
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from nmigen.utils import log2_int
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from nmigen.lib.fifo import SyncFIFO
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from ..cache import *
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from ..isa import Funct3
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from ..wishbone import *
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__all__ = ["DataSelector", "LoadStoreUnitInterface", "BareLoadStoreUnit", "CachedLoadStoreUnit"]
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class DataSelector(Elaboratable):
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def __init__(self):
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self.x_offset = Signal(2)
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self.x_funct3 = Signal(3)
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self.x_store_operand = Signal(32)
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self.w_offset = Signal(2)
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self.w_funct3 = Signal(3)
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self.w_load_data = Signal(32)
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self.x_misaligned = Signal()
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self.x_mask = Signal(4)
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self.x_store_data = Signal(32)
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self.w_load_result = Signal((32, True))
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def elaborate(self, platform):
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m = Module()
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with m.Switch(self.x_funct3):
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with m.Case(Funct3.H, Funct3.HU):
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m.d.comb += self.x_misaligned.eq(self.x_offset[0])
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with m.Case(Funct3.W):
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m.d.comb += self.x_misaligned.eq(self.x_offset.bool())
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with m.Switch(self.x_funct3):
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with m.Case(Funct3.B, Funct3.BU):
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m.d.comb += self.x_mask.eq(0b1 << self.x_offset)
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with m.Case(Funct3.H, Funct3.HU):
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m.d.comb += self.x_mask.eq(0b11 << self.x_offset)
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with m.Case(Funct3.W):
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m.d.comb += self.x_mask.eq(0b1111)
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with m.Switch(self.x_funct3):
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with m.Case(Funct3.B):
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m.d.comb += self.x_store_data.eq(self.x_store_operand[:8] << self.x_offset*8)
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with m.Case(Funct3.H):
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m.d.comb += self.x_store_data.eq(self.x_store_operand[:16] << self.x_offset[1]*16)
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with m.Case(Funct3.W):
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m.d.comb += self.x_store_data.eq(self.x_store_operand)
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w_byte = Signal((8, True))
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w_half = Signal((16, True))
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m.d.comb += [
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w_byte.eq(self.w_load_data.word_select(self.w_offset, 8)),
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w_half.eq(self.w_load_data.word_select(self.w_offset[1], 16))
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]
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with m.Switch(self.w_funct3):
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with m.Case(Funct3.B):
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m.d.comb += self.w_load_result.eq(w_byte)
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with m.Case(Funct3.BU):
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m.d.comb += self.w_load_result.eq(Cat(w_byte, 0))
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with m.Case(Funct3.H):
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m.d.comb += self.w_load_result.eq(w_half)
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with m.Case(Funct3.HU):
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m.d.comb += self.w_load_result.eq(Cat(w_half, 0))
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with m.Case(Funct3.W):
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m.d.comb += self.w_load_result.eq(self.w_load_data)
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return m
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class LoadStoreUnitInterface:
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def __init__(self):
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self.dbus = Record(wishbone_layout)
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self.x_addr = Signal(32)
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self.x_mask = Signal(4)
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self.x_load = Signal()
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self.x_store = Signal()
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self.x_store_data = Signal(32)
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self.x_stall = Signal()
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self.x_valid = Signal()
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self.m_stall = Signal()
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self.m_valid = Signal()
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self.x_busy = Signal()
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self.m_busy = Signal()
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self.m_load_data = Signal(32)
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self.m_load_error = Signal()
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self.m_store_error = Signal()
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self.m_badaddr = Signal(30)
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class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
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def elaborate(self, platform):
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m = Module()
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with m.If(self.dbus.cyc):
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with m.If(self.dbus.ack | self.dbus.err | ~self.m_valid):
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m.d.sync += [
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self.dbus.cyc.eq(0),
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self.dbus.stb.eq(0),
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self.m_load_data.eq(self.dbus.dat_r)
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]
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with m.Elif((self.x_load | self.x_store) & self.x_valid & ~self.x_stall):
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m.d.sync += [
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self.dbus.cyc.eq(1),
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self.dbus.stb.eq(1),
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self.dbus.adr.eq(self.x_addr[2:]),
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self.dbus.sel.eq(self.x_mask),
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self.dbus.we.eq(self.x_store),
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self.dbus.dat_w.eq(self.x_store_data)
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]
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with m.If(self.dbus.cyc & self.dbus.err):
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m.d.sync += [
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self.m_load_error.eq(~self.dbus.we),
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self.m_store_error.eq(self.dbus.we),
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self.m_badaddr.eq(self.dbus.adr)
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]
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with m.Elif(~self.m_stall):
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m.d.sync += [
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self.m_load_error.eq(0),
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self.m_store_error.eq(0)
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]
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m.d.comb += self.x_busy.eq(self.dbus.cyc)
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with m.If(self.m_load_error | self.m_store_error):
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m.d.comb += self.m_busy.eq(0)
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with m.Else():
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m.d.comb += self.m_busy.eq(self.dbus.cyc)
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return m
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class CachedLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
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def __init__(self, *dcache_args):
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super().__init__()
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self.dcache_args = dcache_args
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self.x_fence_i = Signal()
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self.m_load = Signal()
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self.m_store = Signal()
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self.m_flush = Signal()
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def elaborate(self, platform):
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m = Module()
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dcache = m.submodules.dcache = L1Cache(*self.dcache_args)
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x_dcache_select = Signal()
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# Test whether the target address is inside the L1 cache region. We use bit masks in order
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# to avoid carry chains from arithmetic comparisons. This restricts the region boundaries
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# to powers of 2.
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with m.Switch(self.x_addr[2:]):
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def addr_below(limit):
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assert limit in range(1, 2**30 + 1)
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range_bits = log2_int(limit)
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const_bits = 30 - range_bits
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return "{}{}".format("0" * const_bits, "-" * range_bits)
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if dcache.base >= 4:
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with m.Case(addr_below(dcache.base >> 2)):
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m.d.comb += x_dcache_select.eq(0)
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with m.Case(addr_below(dcache.limit >> 2)):
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m.d.comb += x_dcache_select.eq(1)
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with m.Default():
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m.d.comb += x_dcache_select.eq(0)
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m_dcache_select = Signal()
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m_addr = Signal.like(self.x_addr)
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with m.If(~self.x_stall):
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m.d.sync += [
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m_dcache_select.eq(x_dcache_select),
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m_addr.eq(self.x_addr),
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]
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m.d.comb += [
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dcache.s1_addr.eq(self.x_addr[2:]),
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dcache.s1_stall.eq(self.x_stall),
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dcache.s1_valid.eq(self.x_valid),
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dcache.s2_addr.eq(m_addr[2:]),
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dcache.s2_re.eq(self.m_load & m_dcache_select),
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dcache.s2_evict.eq(self.m_store & m_dcache_select),
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dcache.s2_flush.eq(self.m_flush),
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dcache.s2_valid.eq(self.m_valid),
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]
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wrbuf_w_data = Record([("addr", 30), ("mask", 4), ("data", 32)])
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wrbuf_r_data = Record.like(wrbuf_w_data)
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wrbuf = m.submodules.wrbuf = SyncFIFO(width=len(wrbuf_w_data), depth=dcache.nwords)
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m.d.comb += [
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wrbuf.w_data.eq(wrbuf_w_data),
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wrbuf_w_data.addr.eq(self.x_addr[2:]),
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wrbuf_w_data.mask.eq(self.x_mask),
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wrbuf_w_data.data.eq(self.x_store_data),
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wrbuf.w_en.eq(self.x_store & self.x_valid & x_dcache_select & ~self.x_stall),
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wrbuf_r_data.eq(wrbuf.r_data),
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]
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dbus_arbiter = m.submodules.dbus_arbiter = WishboneArbiter()
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m.d.comb += dbus_arbiter.bus.connect(self.dbus)
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wrbuf_port = dbus_arbiter.port(priority=0)
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m.d.comb += [
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wrbuf_port.cyc.eq(wrbuf.r_rdy),
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wrbuf_port.we.eq(Const(1)),
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]
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with m.If(wrbuf_port.stb):
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with m.If(wrbuf_port.ack | wrbuf_port.err):
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m.d.sync += wrbuf_port.stb.eq(0)
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m.d.comb += wrbuf.r_en.eq(1)
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with m.Elif(wrbuf.r_rdy):
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m.d.sync += [
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wrbuf_port.stb.eq(1),
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wrbuf_port.adr.eq(wrbuf_r_data.addr),
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wrbuf_port.sel.eq(wrbuf_r_data.mask),
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wrbuf_port.dat_w.eq(wrbuf_r_data.data)
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]
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dcache_port = dbus_arbiter.port(priority=1)
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m.d.comb += [
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dcache_port.cyc.eq(dcache.bus_re),
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dcache_port.stb.eq(dcache.bus_re),
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dcache_port.adr.eq(dcache.bus_addr),
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dcache_port.sel.eq(0b1111),
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dcache_port.cti.eq(Mux(dcache.bus_last, Cycle.END, Cycle.INCREMENT)),
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dcache_port.bte.eq(Const(log2_int(dcache.nwords) - 1)),
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dcache.bus_valid.eq(dcache_port.ack),
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dcache.bus_error.eq(dcache_port.err),
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dcache.bus_rdata.eq(dcache_port.dat_r)
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]
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bare_port = dbus_arbiter.port(priority=2)
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bare_rdata = Signal.like(bare_port.dat_r)
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with m.If(bare_port.cyc):
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with m.If(bare_port.ack | bare_port.err | ~self.m_valid):
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m.d.sync += [
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bare_port.cyc.eq(0),
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bare_port.stb.eq(0),
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bare_rdata.eq(bare_port.dat_r)
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]
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with m.Elif((self.x_load | self.x_store) & ~x_dcache_select & self.x_valid & ~self.x_stall):
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m.d.sync += [
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bare_port.cyc.eq(1),
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bare_port.stb.eq(1),
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bare_port.adr.eq(self.x_addr[2:]),
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bare_port.sel.eq(self.x_mask),
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bare_port.we.eq(self.x_store),
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bare_port.dat_w.eq(self.x_store_data)
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]
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with m.If(self.dbus.cyc & self.dbus.err):
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m.d.sync += [
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self.m_load_error.eq(~self.dbus.we),
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self.m_store_error.eq(self.dbus.we),
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self.m_badaddr.eq(self.dbus.adr)
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]
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with m.Elif(~self.m_stall):
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m.d.sync += [
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self.m_load_error.eq(0),
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self.m_store_error.eq(0)
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]
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with m.If(self.x_fence_i):
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m.d.comb += self.x_busy.eq(wrbuf.r_rdy)
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with m.Elif(x_dcache_select):
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m.d.comb += self.x_busy.eq(self.x_store & ~wrbuf.w_rdy)
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with m.Else():
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m.d.comb += self.x_busy.eq(bare_port.cyc)
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with m.If(self.m_flush):
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m.d.comb += self.m_busy.eq(~dcache.s2_flush_ack)
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with m.If(self.m_load_error | self.m_store_error):
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m.d.comb += self.m_busy.eq(0)
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with m.Elif(m_dcache_select):
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m.d.comb += [
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self.m_busy.eq(self.m_load & dcache.s2_miss),
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self.m_load_data.eq(dcache.s2_rdata)
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]
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with m.Else():
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m.d.comb += [
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self.m_busy.eq(bare_port.cyc),
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self.m_load_data.eq(bare_rdata)
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]
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return m
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