39 lines
1.4 KiB
Python
39 lines
1.4 KiB
Python
from insn import *
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class rvfi_insn_I_shift(rvfi_insn):
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def __init__(self):
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super(rvfi_insn_I_shift, self).__init__()
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self.insn_padding = Signal(32)
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self.insn_funct6 = Signal(7)
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self.insn_shamt = Signal(6)
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self.insn_rs1 = Signal(5)
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self.insn_funct3 = Signal(3)
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self.insn_rd = Signal(5)
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self.insn_opcode = Signal(7)
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self.misa_ok = Signal(1)
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def ports(self):
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return super(rvfi_insn_I_shift, self).ports()
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def elaborate(self, platform):
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m = super(rvfi_insn_I_shift, self).elaborate(platform)
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# I-type instruction format (shift variation)
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m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
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m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32])
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m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26])
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m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
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m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
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m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
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m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])
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m.d.comb += self.misa_ok.eq(1)
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# default assignments
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m.d.comb += self.spec_rs2_addr.eq(0)
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m.d.comb += self.spec_trap.eq(~self.misa_ok)
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m.d.comb += self.spec_mem_addr.eq(0)
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m.d.comb += self.spec_mem_rmask.eq(0)
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m.d.comb += self.spec_mem_wmask.eq(0)
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m.d.comb += self.spec_mem_wdata.eq(0)
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return m
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