48 lines
1.8 KiB
Markdown
48 lines
1.8 KiB
Markdown
# riscv-formal-nmigen
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A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
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## Dependencies
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- [nMigen](https://github.com/m-labs/nmigen)
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Note that:
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1. Even though this project includes a copy of nMigen, it is highly recommended to remove the copy and install the latest version of nMigen on your system for building this repo
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1. The nMigen package that comes with the [Nix](https://nixos.org/features.html) package manager may not contain the latest changes and therefore may not work with this repo
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1. If you do choose to keep the copy of nMigen provided in this repo anyway, you may need to separately install its dependencies for the build to work:
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- [setuptools](https://pypi.org/project/setuptools/)
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- [pyvcd](https://pypi.org/project/pyvcd/)
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- [Yosys](https://github.com/YosysHQ/yosys)
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- [SymbiYosys](https://github.com/YosysHQ/SymbiYosys)
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## Breakdown
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| Directory | Description |
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| --- | --- |
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| `nmigen` | [nMigen](https://github.com/m-labs/nmigen) |
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| `rvfi` | RISC-V Formal Verification Framework (nMigen port) |
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| `rvfi/insns` | Supported RISC-V instructions and ISAs |
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| `rvfi/cores` | Example cores for verification with riscv-formal-nmigen |
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| `rvfi/cores/minerva` | The [Minerva](https://github.com/lambdaconcept/minerva) core |
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## Build
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### Minerva
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`cd` to the root directory of this project and do:
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```python
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$ python -m rvfi.cores.minerva.verify
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```
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You may see some warning messages about unused `Elaboratable`s and deprecated use of `Simulation` which can be safely ignored.
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## Scope
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Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.
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## License
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See [LICENSE](./LICENSE)
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