115 lines
4.5 KiB
Python
115 lines
4.5 KiB
Python
import argparse
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import warnings
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from nmigen import cli
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from minerva.core import Minerva
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def main():
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parser = argparse.ArgumentParser(formatter_class=argparse.ArgumentDefaultsHelpFormatter)
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parser.add_argument("--reset-addr",
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type=lambda s: int(s, 16), default="0x00000000",
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help="reset vector address")
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parser.add_argument("--with-icache",
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default=False, action="store_true",
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help="enable the instruction cache")
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parser.add_argument("--with-dcache",
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default=False, action="store_true",
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help="enable the data cache")
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parser.add_argument("--with-muldiv",
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default=False, action="store_true",
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help="enable RV32M support")
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parser.add_argument("--with-debug",
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default=False, action="store_true",
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help="enable the Debug Module")
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parser.add_argument("--with-trigger",
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default=False, action="store_true",
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help="enable the Trigger Module")
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parser.add_argument("--with-rvfi",
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default=False, action="store_true",
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help="enable the riscv-formal interface")
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icache_group = parser.add_argument_group("icache options")
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icache_group.add_argument("--icache-nways",
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type=int, choices=[1, 2], default=1,
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help="number of ways")
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icache_group.add_argument("--icache-nlines",
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type=int, default=32,
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help="number of lines")
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icache_group.add_argument("--icache-nwords",
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type=int, choices=[4, 8, 16], default=4,
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help="number of words in a line")
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icache_group.add_argument("--icache-base",
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type=lambda s: int(s, 16), default="0x00000000",
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help="base address")
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icache_group.add_argument("--icache-limit",
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type=lambda s: int(s, 16), default="0x80000000",
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help="limit address")
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dcache_group = parser.add_argument_group("dcache options")
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dcache_group.add_argument("--dcache-nways",
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type=int, choices=[1, 2], default=1,
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help="number of ways")
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dcache_group.add_argument("--dcache-nlines",
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type=int, default=32,
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help="number of lines")
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dcache_group.add_argument("--dcache-nwords",
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type=int, choices=[4, 8, 16], default=4,
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help="number of words in a line")
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dcache_group.add_argument("--dcache-base",
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type=lambda s: int(s, 16), default="0x00000000",
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help="base address")
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dcache_group.add_argument("--dcache-limit",
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type=lambda s: int(s, 16), default="0x80000000",
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help="limit address")
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trigger_group = parser.add_argument_group("trigger options")
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trigger_group.add_argument("--nb-triggers",
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type=int, default=8,
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help="number of triggers")
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cli.main_parser(parser)
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args = parser.parse_args()
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if args.with_debug and not args.with_trigger:
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warnings.warn("Support for hardware breakpoints requires --with-trigger")
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cpu = Minerva(args.reset_addr,
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args.with_icache, args.icache_nways, args.icache_nlines, args.icache_nwords,
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args.icache_base, args.icache_limit,
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args.with_dcache, args.dcache_nways, args.dcache_nlines, args.dcache_nwords,
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args.dcache_base, args.dcache_limit,
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args.with_muldiv,
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args.with_debug,
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args.with_trigger, args.nb_triggers,
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args.with_rvfi)
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ports = [
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cpu.external_interrupt, cpu.timer_interrupt, cpu.software_interrupt,
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cpu.ibus.ack, cpu.ibus.adr, cpu.ibus.bte, cpu.ibus.cti, cpu.ibus.cyc, cpu.ibus.dat_r,
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cpu.ibus.dat_w, cpu.ibus.sel, cpu.ibus.stb, cpu.ibus.we, cpu.ibus.err,
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cpu.dbus.ack, cpu.dbus.adr, cpu.dbus.bte, cpu.dbus.cti, cpu.dbus.cyc, cpu.dbus.dat_r,
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cpu.dbus.dat_w, cpu.dbus.sel, cpu.dbus.stb, cpu.dbus.we, cpu.dbus.err
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]
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if args.with_debug:
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ports += [cpu.jtag.tck, cpu.jtag.tdi, cpu.jtag.tdo, cpu.jtag.tms]
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if args.with_rvfi:
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ports += [
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cpu.rvfi.valid, cpu.rvfi.order, cpu.rvfi.insn, cpu.rvfi.trap, cpu.rvfi.halt,
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cpu.rvfi.intr, cpu.rvfi.mode, cpu.rvfi.ixl, cpu.rvfi.rs1_addr, cpu.rvfi.rs2_addr,
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cpu.rvfi.rs1_rdata, cpu.rvfi.rs2_rdata, cpu.rvfi.rd_addr, cpu.rvfi.rd_wdata,
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cpu.rvfi.pc_rdata, cpu.rvfi.pc_wdata, cpu.rvfi.mem_addr, cpu.rvfi.mem_rmask,
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cpu.rvfi.mem_wmask, cpu.rvfi.mem_rdata, cpu.rvfi.mem_wdata
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]
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cli.main_runner(parser, args, cpu, name="minerva_cpu", ports=ports)
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if __name__ == "__main__":
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main()
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