from insn_SB_type import *

class rvfi_insn_blt(rvfi_insn_SB_type):
    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):
        super(rvfi_insn_blt, self).__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN)
    def ports(self):
        return super(rvfi_insn_blt, self).ports()
    def elaborate(self, platform):
        m = super(rvfi_insn_blt, self).elaborate(platform)

        # BLT instruction
        cond = Signal(1)
        m.d.comb += cond.eq(Value.as_signed(self.rvfi_rs1_rdata) < Value.as_signed(self.rvfi_rs2_rdata))
        next_pc = Signal(self.RISCV_FORMAL_XLEN)
        m.d.comb += next_pc.eq(Mux(cond, self.rvfi_pc_rdata + self.insn_imm, self.rvfi_pc_rdata + 4))
        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b100) & (self.insn_opcode == 0b1100011))
        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
        m.d.comb += self.spec_rs2_addr.eq(self.insn_rs2)
        m.d.comb += self.spec_pc_wdata.eq(next_pc)
        m.d.comb += self.spec_trap.eq(Mux(self.ialign16, next_pc[0] != 0, next_pc[:2] != 0) | ~self.misa_ok)

        # default assignments
        m.d.comb += self.spec_rd_addr.eq(0)
        m.d.comb += self.spec_rd_wdata.eq(0)
        m.d.comb += self.spec_mem_addr.eq(0)
        m.d.comb += self.spec_mem_rmask.eq(0)
        m.d.comb += self.spec_mem_wmask.eq(0)
        m.d.comb += self.spec_mem_wdata.eq(0)

        return m