from insn import *

class rvfi_insn_I_shift(rvfi_insn):
    def __init__(self):
        super(rvfi_insn_I_shift, self).__init__()
        self.insn_padding = Signal(32)
        self.insn_funct6 = Signal(7)
        self.insn_shamt = Signal(6)
        self.insn_rs1 = Signal(5)
        self.insn_funct3 = Signal(3)
        self.insn_rd = Signal(5)
        self.insn_opcode = Signal(7)
        self.misa_ok = Signal(1)
    def ports(self):
        return super(rvfi_insn_I_shift, self).ports()
    def elaborate(self, platform):
        m = super(rvfi_insn_I_shift, self).elaborate(platform)

        # I-type instruction format (shift variation)
        m.d.comb += self.insn_padding.eq(self.rvfi_insn >> 32)
        m.d.comb += self.insn_funct6.eq(self.rvfi_insn[26:32])
        m.d.comb += self.insn_shamt.eq(self.rvfi_insn[20:26])
        m.d.comb += self.insn_rs1.eq(self.rvfi_insn[15:20])
        m.d.comb += self.insn_funct3.eq(self.rvfi_insn[12:15])
        m.d.comb += self.insn_rd.eq(self.rvfi_insn[7:12])
        m.d.comb += self.insn_opcode.eq(self.rvfi_insn[:7])

        m.d.comb += self.misa_ok.eq(1)

        # default assignments
        m.d.comb += self.spec_rs2_addr.eq(0)
        m.d.comb += self.spec_trap.eq(~self.misa_ok)
        m.d.comb += self.spec_mem_addr.eq(0)
        m.d.comb += self.spec_mem_rmask.eq(0)
        m.d.comb += self.spec_mem_wmask.eq(0)
        m.d.comb += self.spec_mem_wdata.eq(0)

        return m