with open('isa_rv32i.py', 'w') as isa_rv32i:
    def fprint(strng):
        print(strng, file=isa_rv32i)
    fprint("# Generated by isa_rv32i_gen.py")
    fprint("from nmigen import *")
    fprint("")
    fprint("class rvfi_isa_rv32i(Elaboratable):")
    fprint("    def __init__(self, RISCV_FORMAL_ILEN=32, RISCV_FORMAL_XLEN=32):")
    fprint("        self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN")
    fprint("        self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN")
    fprint("        self.rvfi_valid = Signal(1)")
    fprint("        self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)")
    fprint("        self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("        self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("        self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("        self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("")
    fprint("        self.spec_valid = Signal(1)")
    fprint("        self.spec_trap = Signal(1)")
    fprint("        self.spec_rs1_addr = Signal(5)")
    fprint("        self.spec_rs2_addr = Signal(5)")
    fprint("        self.spec_rd_addr = Signal(5)")
    fprint("        self.spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("        self.spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("        self.spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("        self.spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))")
    fprint("        self.spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))")
    fprint("        self.spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)")
    fprint("    def ports(self):")
    fprint("        input_ports = [")
    fprint("            self.rvfi_valid,")
    fprint("            self.rvfi_insn,")
    fprint("            self.rvfi_pc_rdata,")
    fprint("            self.rvfi_rs1_rdata,")
    fprint("            self.rvfi_rs2_rdata,")
    fprint("            self.rvfi_mem_rdata")
    fprint("        ]")
    fprint("        output_ports = [")
    fprint("            self.spec_valid,")
    fprint("            self.spec_trap,")
    fprint("            self.spec_rs1_addr,")
    fprint("            self.spec_rs2_addr,")
    fprint("            self.spec_rd_addr,")
    fprint("            self.spec_rd_wdata,")
    fprint("            self.spec_pc_wdata,")
    fprint("            self.spec_mem_addr,")
    fprint("            self.spec_mem_rmask,")
    fprint("            self.spec_mem_wmask,")
    fprint("            self.spec_mem_wdata")
    fprint("        ]")
    fprint("    def elaborate(self, platform):")
    fprint("        m = Module()")
    fprint("")
    # TODO
    fprint("")
    fprint("        return m")

    # For debugging purposes only
    fprint("")
    fprint("test = rvfi_isa_rv32i()")
    fprint("test.ports()")
    fprint("test.elaborate(platform=None)")