from .insn_rv64i_i_type import *

"""
RV64I I-Type Instruction (Load Variation)
"""

class InsnRV64IITypeLoad(InsnRV64IIType):
    def __init__(self, params, mask_shift, funct3, is_signed):
        super().__init__(params)
        self.mask_shift = mask_shift
        self.funct3 = funct3
        self.is_signed = is_signed
    def elaborate(self, platform):
        m = super().elaborate(platform)

        if self.params.aligned_mem:
            addr = Signal(self.params.xlen)
            m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
            result = Signal(8 * self.mask_shift)
            m.d.comb += result.eq(self.rvfi_mem_rdata >> (8 * (addr - self.spec_mem_addr)))
            m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011))
            m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
            m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
            m.d.comb += self.spec_mem_addr.eq(addr & ~(self.params.xlen // 8 - 1))
            m.d.comb += self.spec_mem_rmask.eq(((1 << self.mask_shift) - 1) << (addr - self.spec_mem_addr))
            m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result) if self.is_signed else result, 0))
            m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
            m.d.comb += self.spec_trap.eq(((addr & (self.mask_shift - 1)) != 0) | ~self.misa_ok)
        else:
            addr = Signal(self.params.xlen)
            m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
            result = Signal(8 * self.mask_shift)
            m.d.comb += result.eq(sself.rvfi_mem_rdata)
            m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0000011))
            m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
            m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
            m.d.comb += self.spec_mem_addr.eq(addr)
            m.d.comb += self.spec_mem_rmask.eq((1 << self.mask_shift) - 1)
            m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result) if self.is_signed else result, 0))
            m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
            m.d.comb += self.spec_trap.eq(~self.misa_ok)

        return m