from insn_I import *

class rvfi_insn_lh(rvfi_insn_I):
    def __init__(self):
        super(rvfi_insn_lh, self).__init__()
    def ports(self):
        return super(rvfi_insn_lh, self).ports()
    def elaborate(self, platform):
        m = super(rvfi_insn_lh, self).elaborate(platform)

        # LH instruction
        addr = Signal(32)
        m.d.comb += addr.eq(self.rvfi_rs1_rdata + self.insn_imm)
        result = Signal(16)
        m.d.comb += result.eq(self.rvfi_mem_rdata)
        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (self.insn_funct3 == 0b001) & (self.insn_opcode == 0b0000011))
        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
        m.d.comb += self.spec_mem_addr.eq(addr)
        m.d.comb += self.spec_mem_rmask.eq((1 << 2) - 1)
        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Value.as_signed(result), 0))
        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)
        m.d.comb += self.spec_trap.eq(~self.misa_ok)

        return m