from .insn import *

"""
RV32I I-Type Instruction (Shift Variation)
"""

class InsnRV32IITypeShift(Insn):
    def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, funct6, funct3):
        super().__init__(RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA)
        self.funct6 = funct6
        self.funct3 = funct3
    def elaborate(self, platform):
        m = super().elaborate(platform)

        if self.RISCV_FORMAL_CSR_MISA:
            m.d.comb += self.misa_ok.eq((self.rvfi_csr_misa_rdata & 0) == 0)
            m.d.comb += self.spec_csr_misa_rmask.eq(0)
        else:
            m.d.comb += self.misa_ok.eq(1)

        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct6 == self.funct6) & (self.insn_funct3 == self.funct3) & (self.insn_opcode == 0b0010011) & ((~self.insn_shamt[5]) | (self.RISCV_FORMAL_XLEN == 64)))
        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)

        return m