from functools import reduce from operator import or_ from nmigen import * from nmigen.hdl.rec import * from ...wishbone import wishbone_layout from .dmi import * __all__ = ["BusError", "AccessSize", "DebugWishboneMaster"] class BusError: NONE = 0 TIMEOUT = 1 BAD_ADDRESS = 2 MISALIGNED = 3 BAD_SIZE = 4 OTHER = 7 class AccessSize: BYTE = 0 HALF = 1 WORD = 2 class DebugWishboneMaster(Elaboratable): def __init__(self, debugrf): self.bus = Record(wishbone_layout) self.dbus_busy = Signal() self.sbcs = debugrf.reg_port(DebugReg.SBCS) self.sbaddress0 = debugrf.reg_port(DebugReg.SBADDRESS0) self.sbdata0 = debugrf.reg_port(DebugReg.SBDATA0) def elaborate(self, platform): m = Module() addr = self.sbaddress0.w.value size = self.sbcs.r.sbaccess width = Signal(6) m.d.comb += width.eq((1< AccessSize.WORD): m.d.sync += sberror.eq(BusError.BAD_SIZE) with m.Elif((addr & (1<> addr[:2]*8) & (1<