from insn_I import *

class rvfi_insn_sltiu(rvfi_insn_I):
    def __init__(self):
        super(rvfi_insn_sltiu, self).__init__()
    def ports(self):
        return super(rvfi_insn_sltiu, self).ports()
    def elaborate(self, platform):
        m = super(rvfi_insn_sltiu, self).elaborate(platform)

        # SLTIU instruction
        result = Signal(32)
        m.d.comb += result.eq(self.rvfi_rs1_rdata < self.insn_imm)
        m.d.comb += self.spec_valid.eq(self.rvfi_valid & (~self.insn_padding) & (self.insn_funct3 == 0b011) & (self.insn_opcode == 0b0010011))
        m.d.comb += self.spec_rs1_addr.eq(self.insn_rs1)
        m.d.comb += self.spec_rd_addr.eq(self.insn_rd)
        m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, result, 0))
        m.d.comb += self.spec_pc_wdata.eq(self.rvfi_pc_rdata + 4)

        return m